Modeling for stuck faults in cmos non-threshold logic (NTL) combinational circuits

Abstract

In this paper, a transistor model is presented for CMOS Non Threshold Logic (NTL) combinational circuits. This model employs the logic transistor function (LTF) to examine the behavior of CMOS Non Threshold Logic (NTL) circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the logic values 0, 1, I , M, where, I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults can be analyzed by this model. Primitive D-cubes of the fault can be extracted for a specified subcircuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used. Algorithms that were developed for Pseudo NMOS combinational circuits can be directly applied to generate test vectors.