Negative Vth Shift Research Articles

Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs

In this study, we evaluated and characterized the effects of various proton irradiation energies and fluences on the electrical characteristics of SiC MOSFETs using a proton accelerator. The devices under test (DUTs) were fabricated utilizing 1.2 kV SiC MOSFET processes. To assess the impact of total ionizing dose (TID) and displacement damage (DD) on SiC MOSFETs, the DUTs were exposed to protons irradiation at energies of 30 MeV and 100 MeV, under ambient temperature conditions. Additionally, we examined the radiation hardness of DUTs under varying proton fluences, including 1 × 1012 cm−2, 1 × 1013 cm−2, 5 × 1013 cm−2, and 1 × 1014 cm−2.The results demonstrate that the threshold voltage (Vth) of the irradiated devices exhibited a negative shift, attributable to radiation-induced positive oxide trapped charges. This negative shift in Vth, coupled with the accumulation of positive trapped charges in the field limiting ring (FLR) oxide, resulted in augmented output currents and diminished breakdown voltage (BV) values. A significant reduction in current, ranging from 70% to 99%, was observed in the DUT subjected to irradiation at of 30 MeV and 1 × 1014 cm−2, highlighting the influence of DD. Conversely, irradiation at 100 MeV primarily revealed TID effects, characterized by a negatively shifted Vth. The on-state current at a gate voltage of 10 V and a drain voltage of 5 V of the DUT with irradiation of 100 MeV and 1 × 1014 cm−2 was a higher than that of DUT without irradiation because of a reduction of Vth.

Total Ionizing Dose (TID) Effects on the 1.2 kV SiC MOSFETs under Proton Irradiation

In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (Vth) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in Vth and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Temperature Dependent Anomalous Threshold Voltage Modulation of a-IGZO TFT by Incorporating Variant Gate Stresses

Amorphous indium gallium zinc oxide (a-IGZO) has recently made significant advancement as a key material for electronic component design owing to its compatibility with complementary metal oxide semiconductor technologies. A comprehensive analysis of reliability-related issues is required to determine the true potential of a-IGZO-based devices for next-generation electronics applications. To address this objective, we electrically characterize scaled-channel a-IGZO thin film transistors (TFTs) under positive bias (temperature) stress (PB(T)S). Both PBS and PBTS are characterized by positive and negative Vth shift, respectively, during the various gate stresses. In particular, the negative Vth shift is explained by the generation of donor-like traps stimulated by ionization of oxygen vacancy/hydrogen at elevated temperature. The TFTs exhibit relatively decent stability during the PBS operation. The analysis of devices with variant channel dimensions implies that long-channel devices exhibit relatively higher stability and performance compared to the short-channel ones. We also observe that the Vth can be controllably adjusted by employing the top gate (TG) with bottom gate sweep. Moreover, the stress-induced partial recovery mechanism is experimentally observed owing to detrapping of charges. Generally, the reported results infer a perceptive understanding of scaled-channel a-IGZO-TFTs which helps with shaping performance-enhancement strategies.

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Bias stress stabilities of PMMA-passivated indium-gallium-zinc-oxide thin-film transistors after 100 °C steam exposure

Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics and bias stress stabilities were changed after being exposed on 100 °C steam. There were negative Vth shifts on the transfer curves of the steam-exposed IGZO TFTs. Our XPS analysis revealed that the negative ΔVth was related to the steam-induced H2O molecules throughout the IGZO films, which acted as electron donors to introduce more electrons in the front channel. Under PBS, the steam-exposed IGZO TFTs showed an abnormal negative Vth shift while the un-exposed IGZO TFTs showed negligible Vth shift. This abnormality was ascribed to the electrons released from steam-induced H2O molecules, which render the conductive path more easily opened. Under NBS, the steam-exposed IGZO TFT presented larger negative Vth shift than the un-exposed TFT. This result was interpreted in terms of the steam-induced donor states (H2O molecules) near or at channel/insulator interface. Under PBTS and NBTS, the changes in Vth for steam-exposed TFTs were similar to those for un-exposed TFTs. Such a similarity indicates that steam exposure had no effects on NBTS and PBTS stabilities. It was understood in terms that the steam-induced H2O+ recombined with the electrons released from the steam-induced H2O molecules under bias stress, forming H2O to compensate the thermally-induced H2O adsorption. Our results suggest that one-micron-thick PMMA passivation layer enabled to protect IGZO TFTs from H2O in a normal environment, but it provided inadequate protection in a harsh environment. Therefore, a thicker PMMA passivation layer should be considered.

Post-annealing effect of low temperature atomic layer deposited Al2O3 on the top gate IGZO TFT

Electronical properties of top gate amorphous InGaZnO4 thin film transistors (TFTs) could be controlled by post-annealing treatment, which has a great impact on the Al2O3 insulator. To investigate the effect of post-annealing on Al2O3, Al/Al2O3/p-Si MOS capacitoras with Al2O3 films treated under various post-deposition annealing (PDA) temperature were employed to analysis the change of electrical properties, surface morphology, and chemical components by electrical voltage scanning, atomic force microscope (AFM), and x-ray photoelectron spectroscopy (XPS) technologies. After PDA treatment, the top gate TFTs had a mobility about 7 cm2 V−1 s−1 and the minimum subthreshold swing (SS) about 0.11 V/dec, and the threshold voltage (V th) shifted from positive direction to negative direction as the post-annealing temperature increased. Electrical properties of MOS capacitors revealed the existence of positive fixed charges and the variation of trap state density with increasing PDA temperature, and further explained the change of negative bias stress (NBS) stability in TFT. AFM results clarified the increased leakage current, degraded SS, and NBS stability in MOS capacitors and TFTs, respectively. XPS results not only illuminated the origin of fixed charges and the trap density variation with PDA temperatures of Al2O3 films, but also showed the O and H diffusion from Al2O3 into IGZO during post-annealing process, which led to the deviation of V th, the change of current density, and the negative V th shift after positive bias stress in TFTs.

Impact of high-temperature operating lifetime tests on the stability of 0.15 μm AlGaN/GaN HEMTs: A temperature-dependent analysis

We present a detailed analysis of the effect of low- and high-temperature operating lifetime (LTOL and HTOL) carried out on 0.15 μm GaN HEMTs for RF applications. Based on several stress experiments carried out at different temperature levels, a) we demonstrate the existence of two degradation modes consisting, respectively, in the negative and positive shift in the threshold voltage; b) temperature-dependent I-V measurements indicate that no modification in the Schottky barrier height takes place after stress; c) the negative VTH shift is ascribed to the temperature- and field-assisted de-trapping of electrons from the passivation/AlGaN stack under the gate, consistent with previous reports; d) the positive VTH shift, which only occurs at high temperature levels, is ascribed to the trapping of hot electrons, possibly at the AlGaN/SiN interface.

Temperature dependent characteristics of β -Ga2O3 FinFETs by MacEtch

Understanding the thermal stability and degradation mechanism of β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial for their high-power electronics applications. This work examines the high temperature performance of the junctionless lateral β-Ga2O3 FinFET grown on a native β-Ga2O3 substrate, fabricated by metal-assisted chemical etching with Al2O3 gate oxide and Ti/Au gate metal. The thermal exposure effect on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and specific on-resistance (Ron,sp), as a function of temperature up to 298 °C, is measured and analyzed. SS and Ron,sp increased with increasing temperatures, similar to the planar MOSFETs, while a more severe negative shift of Vth was observed for the high aspect-ratio FinFETs here. Despite employing a much thicker epilayer (∼2 μm) for the channel, the high temperature performance of Ion/Ioff ratios and SS of the FinFET in this work remains comparable to that of the planar β-Ga2O3 MOSFETs reported using epilayers ∼10–30× thinner. This work paves the way for further investigation into the stability and promise of β-Ga2O3 FinFETs compared to their planar counterparts.

Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs

Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

9.2: Mechanism of H2O‐induced Instability of Self‐Aligned Top‐Gate Amorphous InGaZnO TFTs

The influence of H2O on self‐aligned top‐gate (SATG) a‐ InGaZnO thin‐film transistor (TFT) was systematically investigated by performing the high‐temperature high‐humidity (HTHH) test (50 °C, 80% RH). Though initial electrical characteristics were well maintained, the stability under positive bias stress (PBS) was considerably deteriorated, including an abnormal negative Vth shift, degraded SS, and increased off current. The mechanism of H2O‐induced instability was proposed to be the dissociation of H2O molecules and the migration of hydrogen (H) atoms into the a‐IGZO channel. The hydrogen diffusion and doping effects in SATG a‐IGZO TFTs were further proved by SiNx‐passivated TFTs with regulated H content in SiNx layers.

Impact of the Source/Drain Electrode Process on the Mobility-Threshold Trade-Off for InSnZnO Thin-Film Transistors

In this work, the source/drain (S/D) electrode process is considered to have a great impact on the mobility (μFE)–threshold (Vth) trade-off for high-mobility amorphous oxide semiconductor (AOS) thin-film transistors. High-mobility AOS materials have worse oxygen-fixation ability compared to InGaZnO. In this work, we show that this is the case for the Mo S/D electrode process on InSnZnO channels and has a great impact on the mobility-threshold trade-off. Oxygen vacancy gradients are observed in the depth profile X-ray photoelectron spectroscopy analysis on InSnZnO after Mo S/D deposition and show a bigger change in oxygen vacancies (VO) between the surface and inner layers and thicker compared to InGaZnO. This leads to an obvious negative shift in Vth or even no switching characteristic. Postprocessing such as oxygen-plasma treatment can make Vth positive but degrade the μFE. In situ replenishing oxygen via adopting ITO S/D electrodes deposited in an oxygen-containing atmosphere facilitates the achievement of excellent overall electrical characteristics, with μFE up to 87.1 cm2/Vs, Vth ∼ −0.64 V, and Ion/Ioff ∼ 2.3 × 108.

Capacitance-Dependent VTH Instability Under a High dVg/dt Event in p-GaN Power HEMTs

In this work, we report that the VTH stability in p-GaN power HEMTs under a high dVg/dt event is highly correlated with the capacitance for the first time. The different dVg/dt event is performed by using fast sweep characterization with sweeping time (tsweep) varied from 10ms to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~\mu \text{s}$ </tex-math></inline-formula> . As the tsweep is decreased, i.e., high dVg/dt, p-GaN HEMTs show a negative VTH shift and a high measured gate current. The higher measured gate current is mainly due to the displacement current with respect to a high dVg/dt. To further understand the impacts of capacitance on VTH stability, p-GaN power HEMTs are connected with different additional capacitance (Cadditional) between gate-to-source terminals. The results indicate that the negative VTH shift and the gate current are highly correlated with the Cadditional, i.e., a large negative VTH shift and a high measured gate current in the device with a large Cadditional, suggesting that the charging capacitance caused by the displacement current during a high dVg/dt event can influence the VTHstability. Therefore, the optimization of the capacitance is crucial to improve the VTH stability during a high-speed gate operation.

Threshold voltage instability and hysteresis in gamma-rays irradiated 4H-SiC junction field effect transistors

High dose irradiation effects of gamma-rays up to 17 MGy (H2O) on 4H-SiC junction field effect transistors (JFETs) were investigated. Due to the irradiation, gradual positive threshold voltage (Vth) shift as high as 0.5 V and continuous decrease in transconductance gm were observed. In addition, Vth instability and hysteresis appeared for the irradiated JFETs when the gate voltage (VG) sweep direction, sweep interval, i.e., averaged sweeping rate, sweep range, and delay time were changed. Increase of VG interval attributed to positive Vth shift for both forward and reverse directions, whereas narrowing of sweep range and increase of delay time resulting in a more noticeable negative shift of Vth for the reverse direction. Such Vth hysteresis indicates that capture and release of carriers predominantly took place via hole traps formed around the gate region due to high dose gamma-ray irradiation.

Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to a positive gate stress bias. Experimental analysis of the threshold voltage transients indicates that both electron and hole trappings take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing–decreasing–increasing pattern. At low/moderate stress fields (&amp;lt;7 MV/cm), the electron trapping kinetics responsible for a positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, which explains the logarithmic degradation kinetics. In the high field regime (&amp;gt;8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field, and generate holes through impact ionization (II) or anode hole injection. These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Stability of the threshold voltage in fluorine-implanted normally-off AlN/GaN HEMTs co-integrated with commercial normally-on GaN HEMT technology

Fluorine ion migration in normally-off AlN/GaN HEMTs fabricated by fluorine ion plasma implantation technology is evidenced. Devices under test are co-integrated into the OMMIC commercial D006GH/D01GH MMIC process, providing fluorine-free normally-on HEMTs. Gate reverse bias step-stress experiment at a drain fixed voltage of 0 V, carried out as well on normally-on ones as on normally-off ones, shows a permanent negative shift in the threshold voltage Vth of normally-off devices only. Vth degradation is starting at a VGS,stress of −8 V, with a negative shift from 0 V to −0.4 V at VGS,stress = −30 V, while the transconductance gm and gm,max remains unchanged prior to breakdown that occurred at VGS,stress ranging between −26 and −32 V. Since the positive threshold voltage of these devices is induced by F-ions dose and position, the above result suggests a possible drift of F-ions away from the 2DEG channel. A field-assisted migration mechanism of fluorine ions is proposed and supported by the absence of Vth degradation in fluorine-free normally-on devices.

Influence of the carrier behaviors in p-GaN gate on the threshold voltage instability in the normally off high electron mobility transistor

Threshold voltage (VTH) instability has been studied in the as-fabricated p-GaN gated enhancement-mode high electron mobility transistors (p-GaN E-HEMTs) under a positive gate stress. A negative VTH shift (ΔVTH) obtained by dynamic measurement has been observed more severely when compared to the static one. The VTH deviation is attributed to the complicated influence of carrier transport behaviors in the p-GaN gate. The impacts of hole accumulation, trapping, and consumption on the VTH instability and drain current variation can be effectively distinguished according to the transfer characteristics obtained from the pulse I–V measurement. Moreover, the density of hole traps in the p-GaN gate is estimated to be around ∼2 × 1011 cm−2 by the capacitance–voltage measurement, and the energy level is calculated to be around EV + 0.62 eV by fitting the recovery curve of gate current after positive gate bias. This study focusing on the in-depth influence of different carrier behaviors on the gate performance can help with the understanding and further improvement of the dynamic instability and reliability of the GaN-based HEMTs.

Flexible high-performance organic thin film transistors and PMOS inverters: Trap controlled grain boundaries and contact resistance effect in different channel length devices

Printed high-performance organic thin film transistors (OTFTs) are fabricated on flexible polyethylene naphthalate (PEN) substrate for low-voltage operation. Gate, source and drain electrodes are inkjet-printed using conductive silver ink, while chemical vapor deposition grown parylene is used as dielectric layer. We used a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo[1,2-b;4,5-b′]dithiophene (DTBDT-C6) and polystyrene (PS), for active p-type organic semiconducting material, and deposited by a dispenser system to achieve 0.66 cm2/Vs mobility at VGS = −6 V. For a set of 30 OTFT devices, the uniformity in device characteristics is illustrated by plotting the histograms for on current, mobility, and threshold voltage (VTh). Mobility decrease for small channel length due to greater contribution of contact resistance, while negative VTh shift occurs because of the generation of hole traps at dielectric-semiconductor interface attributed to moisture present. Electron traps on grain boundaries of the active semiconducting layer causes positive shift in VTh. By using these high mobility OTFT devices, two different low-voltage operation PMOS (P-channel metal-oxide-semiconductor) inverters are fabricated for which high signal gain value of 24.86 is achieved at VDD = −5 V.

P‐9: Understanding Diffusion Behaviors of Light Elements in OLEDs

In the OLED panel, we have been investigated to understand diffusion behaviors of light element in various perspectives. It has evaluated by using advanced analytical tools such nano‐SIMS. we could find the diffused hydrogen from insulating film in channel area of bad sample. Increased hydrogen is directly attributed to the negative Vth shift. Also, we make the cross sectional sample and find the diffusion source of internal outgassing using the cross‐sectional Ion Mapping analysis method.