Negative Capacitance FET Research Articles

Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO<sub>2</sub> used as an insulator decreases.</p> </abstract>

Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits.

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic ( IDS - VDS ) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias ( VBB ). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to VBB for designing a current mirror. Results show that the output current ( IOUT ) variation due to VDS reduces from ~8% to ~2% with VBB . We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS - VDS . We have also explored the device scaling effect on the amplifier gain and found that ~ 2.23× gain can be increased with smaller channel length and higher device width.

Design Space of Negative Capacitance in FETs

Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk MOSFET architectures. The impact of thickness variation of the ferroelectric on the DC characteristics has been deeply investigated. The model precisely estimates a critical thickness of ferroelectric at instability conditions before the device goes into the hysteresis regime. Explicit relationships have been driven for hysteresis voltages which can be used as a general guideline for technology optimization of negative capacitance FETs.

Improved Tradeoff Between Subthreshold Swing and Hysteresis for MoS2Negative-Capacitance FETs by Optimizing Gate-Stack of Hf1−xZrxO2/Al2O3

MoS₂ negative-capacitance field-effect transistors (NCFETs) with a gate-stack of Hf₁₋ₓZrₓO₂/Al₂O₃ are fabricated, and the effects of the Zr content and the thickness of the stacked gate on electrical performance of the devices are investigated. It is found that a large improvement of device performance can be achieved by optimizing these parameters, e.g., using 6-nm Hf $_{0.5}$ Zr $_{0.5}$ O₂ (Zr content of 50%) as a ferroelectric layer and 2-nm Al₂O₃ as a matching layer, the relevant MoS₂ NCFET exhibits the excellent electrical characteristics: a low subthreshold swing (SS) of 31.4 mV/dec, a smaller counterclockwise hysteresis of ~75 mV, and a high on/off current ratio of 3.26 x 10⁶. The involved mechanisms lie in that: 1) an enhanced remnant polarization leads to low SS and 2) changing the thickness of the Hf₁₋ₓZrₓO₂ and Al₂O₃ can adjust the magnitude of ferroelectric capacitance and MOS capacitance to realize a reasonable match between both.

Negative capacitance FETs for energy efficient and hardware secure logic designs

Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness (tfe) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with tfe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with tfe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET (tfe = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with tfe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with tfe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with tfe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).

MoS2 negative-capacitance transistors with steep slope and negligible hysteresis by using monolayer Al1-xZrxOy as gate dielectric plus NH3-plasma treatment

Although ferroelectric material is highlighted for its negative capacitance (NC) effect integrated into MoS2 devices, it usually needs a dielectric layer to provide positive capacitance, which is not conducive to scaling down of transistors. In this work, a monolayer Al1-xZrxOy is used as the gate dielectric to fabricate back-gated MoS2 negative-capacitance FETs (NCFETs), in which host Al2O3 exhibits a positive capacitance and the embedded ZrO2 crystals formed through rapid thermal anneal at 550℃ exhibit a NC effect. By optimizing the Zr content in the Al1-xZrxOy thin film, an enhanced ferroelectricity and a reasonable match between the negative capacitance and the positive capacitance have been achieved for the Al0.93Zr0.07Oy thin film, resulting in excellent device performances: small subthreshold swing (SS) of 28 mV/dec and high on/off current ratio of 6.4 × 107. Moreover, after the Al0.93Zr0.07Oy thin film is suffered from a remote NH3-plasma treatment, its ferroelectricity and NC effect are further enhanced due to the reduction of oxygen vacancies and the improvement of interface quality, thus boosting the performance of the relevant NCFET: the SS is lowered to 18 mV/dec, where the sub-60 mV/dec SS spans almost three orders of Id (drain current) magnitude, the hysteresis is reduced to 25 mV and the driving current is 30% higher than that of the untreated sample. Therefore, the Al0.93Zr0.07Oy thin film with the NH3-plasma treatment as the gate dielectric of MoS2 NCFET has a great potential in achieving the steep-slope, free-hysteresis and low power-consumption performances.

Modeling of the Gate Tunneling Current in MFIS NCFETs

In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance—a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from Sentaurus 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Investigation of time domain characteristics of negative capacitance FinFET by pulse-train approaches

The HfO2-based ferroelectric field effect transistors (FeFET) have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits. This article systematically investigates the transient response of negative capacitance (NC) fin field-effect transistors (FinFETs) through two kinds of self-built test schemes. By comparing the results with those of conventional FinFETs, we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain. Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater (about 80% with NC NMOS) than the on-state current of the conventional transistor, indicating the great potential of the NC FET for future high-frequency applications.

Effect of Negative Capacitance in Partially Ground Plane based SELBOX FET on Capacitance Matching and SCEs

Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferro-electric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(Ec) and remnant polarization(PR) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the RPE factor, which is the ratio of PR to Ec, is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects (Vth rolloff and DIBL) and thickness of the ferro-electric (tfe) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 103 times better \(\frac {\mathrm {I}_{\text {ON}}}{\mathrm {I}_{\text {OFF}}}\) ratio over FDSOI NCFET. For optimized value of ferro-electric parameters average SS for proposed device is found as 50 mV/decade at tfe = 5nm which is lesser than FDSOI NCFET (56 mV/decade).

PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits

For the first time, we demonstrate an optimization technique to synthesize circuits in the Negative Capacitance FET (NCFET) technology. NCFET is a rapidly emerging technology to replace the currently employed CMOS technology due to its profound ability to overcome the fundamental limit in scaling along with its full compatibility with the existing fabrication process. This is achieved by replacing the traditional transistor gate dielectric with a ferroelectric layer that manifests itself as a Negative Capacitance (NC), which magnifies the electric field. As a result, NCFET-based circuits can operate at a higher clock frequency without the need to increase the operating voltage. NC breaks one of the fundamental laws in physics in which the total capacitance of two capacitors connected in series becomes larger–instead of smaller in ordinary capacitors– than each of them. This could lead to sub-optimal netlists, suffering from significant increase in dynamic power and IR-drops. To suppress that, we employ the relation between delay decrease and capacitance increase of gates w.r.t ferroelectric thickness. Our technique takes an optimized netlist, obtained from commercial EDA tools, and then selectively determines the optimal ferroelectric thickness for each gate in the netlist, so that the maximum performance provided by NCFET is still achieved while the dynamic power is considerably decreased (45% on average), i.e., no trade-offs . Particularly, our technique enables the full exploitation of the performance benefits originating by NCFET, at a significantly lower (power) cost. Compared to state of the art, our technique decreases the energy-delay-product of circuits by 25% on average and reduces the deleterious effects of IR-drop by 56%. Hence, efficiency and reliability of circuits are improved without any loss in the obtained performance from NCFET.

Small signal model and analog performance analysis of negative capacitance FETs

In this paper, a small-signal model of Negative Capacitance FETs (NCFETs) is developed and the analog performance of NCFETs is studied using the developed model. A new ferroelectric factor K is introduced to capture the ferroelectric gain in NCFETs as compared to traditional small signal MOSFET/FinFET models. Using our new NCFET small-signal model, we show analog design trade-offs between various analog benchmarks such as gain, bandwidth, cut-off frequency, and linearity. Additionally, the developed model is used to demonstrate trade-offs in NCFET analog performance as ferroelectric parameters are changed. Results show that if pushed for a higher intrinsic gain via thicker Fe layers in NCFETs, the linearity of the device suffers. This reveals inherent device level trade-off in NCFETs for analog circuit performance.

Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NM $_{M}$ ) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization ( ${P}_{r}$ ) and coercive electric ( ${E}_{C}$ ) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states.

Direct Measurement of Transient Charging and Dipole Alignment Speed in Ferroelectric Hf0.5Zr0.5O2 Gate Dielectric Using Graphene FETs

AbstractA novel method to analyze the ferroelectric switching behaviors of Hf0.5Zr0.5O2 (HZO) gate dielectric is developed using the unique charge response characteristics of graphene field effect transistor (GFET). The linear density of state of graphene in a low Vg region enables a detailed transient analysis of the effects of transient charging and dipole switching. The trans‐conductance of GFET with ferroelectric HZO is observed to be increased by 610% in DC measurement with a minimal hysteresis as reported for negative capacitance FET. However, fast pulse I–V analysis reveals that the improved swing and small hysteresis of GFET with ferroelectric HZO are the result of compensation between the bulk charge trapping and dipole charges.

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU

Recent breakthroughs in Neural Networks (NNs) led to significant accuracy improvements of several machine learning applications such as image classification and voice recognition. However, this accuracy improvement comes at the cost of an immense increase in computation demands. NNs became one of the most common and computationally intensive workloads in today's datacenters. To address these computational demands, Google announced in 2016 the Tensor Processing Unit (TPU), an advanced custom ASIC accelerator for NN inference. Two new TPU versions (v2 and v3) followed in 2017 and 2018 that support also training. Google TPUv3 packs an immense processing power ( <inline-formula><tex-math notation="LaTeX">$\mathrm{90TFLOPS}$</tex-math></inline-formula> per chip) in a tiny and condensed area, leading to very high on-chip power densities and thus excessive temperature. In this article, superlattice thermoelectric cooling, which is one of the emerging on-chip cooling, is considered as an advanced cooling example for Google TPU and we investigate the impact of Negative Capacitance FET (NCFET), which is one of the recent emerging technologies, on the cooling and efficiency of TPU. Through full-chip design, of the computational core of the TPU, based on <inline-formula><tex-math notation="LaTeX">$14\mathrm{nm}$</tex-math></inline-formula> Intel FinFET technology and multiphysics temperature simulations, we demonstrate that NCFET can significantly minimize the required cooling-cost. More than 4000 NCFET configurations are evaluated in order to traverse the entire design space defined by the thickness of the ferroelectric layer of NCFET, the operating voltage, cooling, and the operating frequency, in addition to all possible FinFET's configurations. Moreover, our experimental evaluation shows that by eliminating the cooling cost, NCFET delivers 2.8x higher efficiency compared to the conventional FinFET baseline.

Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Savg</sub> ), off current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ), and on current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap.

Near-zero computing using NCFET for IoT applications

The energy consumption of the devices or circuits built on the IoT's is becoming a significant concern with the complementary metal oxide semiconductor (CMOS) technology scaling. To reduce energy consumption, supply voltage (VDD) scaling has proved to be an effective technique with near-threshold/subthreshold computations depicting the endpoint of voltage scaling. This paper discusses how the near-zero computing (NZC) is achieved by scaling the VDD beyond the subthreshold regime using the negative capacitance FET (NCFET) to enable IoT with beyond CMOS features. After characterising the NCFET for near zero operation, the basic computational circuits: logic gates and 1-bitfull adder circuit are designed and simulated using NCFET at near-zero VDD of 0.1 V. In comparison with the CMOS counterparts, the NCFET logic designs have achieved significant improvements and is found that the NCFET logic results in more than 54%, 68%, 85%, and 95% savings in power, delay, energy, and EDP respectively.

Effects of Temperature on the Performance of Hf₀.₅Zr₀.₅O₂-Based Negative Capacitance FETs

There arises the growing interest of negative capacitance field effect transistors (NCFETs) for low-power applications, however, temperature as an inevitable influencing factor, its effects on NCFETs require more research for practical applications. In this work, we fabricated Hf0.5Zr{0.5}O{2}(HZO) based NC p-channel FETs and developed a corresponding TCAD simulation deck to study the temperature impact. DC characteristics of NCFETs and its baseline MOSFETs at the common operation temperature range (−50 to 85°C) are measured and simulated. With the increase of temperature, NCFET subthreshold slope (SS) increases much faster than kT / ${q}$ demonstrating pyroelectric effect, and exceeds kT / ${q}$ at ~350K and baseline MOSFETs at ~360K. Similarly, its on-current decreases more rapidly than baseline devices. Finally, we explained the temperature characteristics of NCFET with the help of a developed model through Landau-Khalatnikov (L-K) theory and temperature dependent internal gain ( $\text{A}_{V}$ ).

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET Including Quantum Confinement Effects

An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fe</sub> ) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fe</sub> increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Impact of body-biasing for negative capacitance field-effect transistor

In this study, the body-bias effects on negative capacitance FET (NCFET) are analyzed using technology computer-aided design (TCAD) device simulation with drift-diffusion model and Landau-Khalatnikov. To understand the physical origin the effects, electrical characteristics are evaluated with various ferroelectric (FE) layer thickness for NCFET as compared to the conventional MOSFET. With thicker FE layer, the total capacitance (C Total) becomes larger, while MOS capacitance (C MOS) is sustained, leading to voltage amplification because the difference between C FE and C MOS gets smaller. It gives the strong gate controllability and less sensitivity for threshold voltage (V TH) according to body-bias variations unlike the conventional MOSFET. Moreover, it is confirmed that the surface band-bending at the interface of NCFET is rarely changed with changing body-bias from 0V to −3V.