Negative Bias Temperature Instability Model Research Articles

Time-dependent statistical NBTI model for aging assessment in circuit level implemented with open model interface

As technology nodes continue to shrink, the impact of aging problems on devices has become increasingly important. One significant aging problem that affects device characteristics and circuit performance is Negative Bias Temperature Instability (NBTI). Under small-size conditions, fluctuations in device parameters such as threshold voltage due to aging are not negligible. To capture these fluctuations, an improved statistical model has been proposed. The time-dependent statistical model accounts for the average change in the number of charged defects due to NBTI and enables the evaluation of degradation fluctuations over time. The model prediction of the threshold voltage degradation of devices in advanced technology is verified with different measured data. Furthermore, the model is implemented with the Open Model Interface (OMI) for the circuit-level degradation simulation, taking advantage of OMI's convenience and compatibility with different circuit simulators. The integration of the proposed model into the OMI benefits in predicting the degradations difference among the transistors in the circuits, reducing the overestimation of aging degradation compared to the methods that assume every transistor experiences the same and worst degradation.

Comparative analysis of NBTI modeling frameworks BAT and Comphy

The Compact-Physical (Comphy) framework is tested against the experimental Negative Bias Temperature Instability (NBTI) data. A cost-function based optimizer is used for obtaining the parameters of Comphy. The ultrafast (10 μs delay) measured threshold voltage shift (ΔVT) during and after NBTI stress at various stress (VGSTR) and recovery (VGREC) bias, temperature (T) and stress time (tSTR), and mixed AC–DC stress using random VGSTR, VGREC, pulse duty cycle (PCD) and frequency (f) are used to test the model framework. The BTI Analysis Tool (BAT) framework, for which data from previous work is used, and Comphy are compared.

An Investigation of Field Reduction Effect on NBTI Parameter Characterization and Lifetime Prediction Using a Constant Field Stress Method

The impact of the field reduction effect on negative bias temperature instability (NBTI) parameter characterization and lifetime prediction was quantitatively studied in p-MOSFETs with a sub-1 nm equivalent oxide thickness (EOT). By comparing NBTI results under constant field stress and constant voltage stress, the field reduction effect was found to become severer at higher VG-STR and ${T}$ and cause a reduction in the voltage acceleration factor (VAF) at higher VG-STR and a reduction in activation energy EA at higher ${T}$ under constant voltage stress. To accurately evaluate NBTI lifetime, a modified NBTI model with field reduction correction (FRC) was proposed, and the 10-year NBTI degradation of a 32-stage ring oscillator was simulated. The results showed that the conventional model without including FRC had a worse prediction capability and overestimated frequency degradation for a ring oscillator. It is necessary to use an NBTI model with FRC for NBTI lifetime prediction of devices with a sub-1 nm EOT.

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency.

Unified Quantum and Reliability Model for Ultra-Thin Double-Gate MOSFETs

This paper presents a unified two-dimensional (2D) threshold voltage model for lightly doped symmetrical double-gate p-channel MOSFETs including quantum confinement effects and negative bias temperature instability (NBTI). The proposed model has been derived by solving the two-dimensional Poisson equation to obtain the NBTI potential model and the one-dimensional Schrodinger equation together with the 2D Poisson equation to obtain the quantum confinement model. The quantum expression was subsequently embedded in the NBTI solution to reach a unified model for both quantum confinement and NBTI. The model is simple and continuous, thereby ensuring compatibility for insertion in Verilog-A based device simulators. The effect of stress time on the degradation of the threshold voltage has been measured over a 10 year period. The accuracy of the model has been validated through comparisons with both 2D numerical simulations and experimental data. The results show matching within ±3% for channel lengths down to 7 nm and silicon thicknesses of 5 nm at 1 GHz operation after 10 years.

Model of NBTI combined with mobility degradation * * Project supported by the Shenzhen Science and Technology Project (Nos. ZDSYS201703031405137, JCYJ20170810163407761, (JCYJ20170818114156474), the PhD Start-up Fund of Natural Science Foundation of Guangdong Province (No. 2015A030310499), and the China Postdoctoral Science Foundation Funded Project (No. 2015T80023).

The mobility degradation induced by negative bias temperature instability (NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after long-term operation. In this paper, the mobility degradation is modeled in combination with the universal NBTI model. The coulomb scattering induced by interface states is revealed to be the dominant component responsible for mobility degradation. The proposed mobility degradation model fits the measured data well and provides an accurate solution for evaluating coupling of NBTI with HCI (hot carrier injection) and SHE (self-heating effect), which indicates that mobility degradation should be considered in long-term circuit aging simulation.

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements

With the scaling of CMOS technology, negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD) are serious issues for transistors. Normally, degradation due to NBTI and GOBD are modeled based on test structure data during process development and monitored with embedded test structures in product die. In this paper, we present a method to determine NBTI and GOBD model parameters through I/O measurements. This work targets products that do not include embedded test structures for wearout monitoring. The ground and power supply bounce signals are used for the calculation of delay and amplitude shifts, which in turn estimate threshold voltage shifts due to NBTI and leakage resistance decreases from gate dielectric degradation. From this data, the NBTI and GOBD parameters are estimated. We calculate the lifetime for each chip individually using calibrated NBTI and GOBD models. The methodology enables the extraction of NBTI and GOBD model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that are more or less vulnerable to NBTI and GOBD.

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

Difference analysis method for negative bias temperature instability lifetime prediction in deeply scaled pMOSFETs

The fluctuation significantly affects the lifetime prediction of negative bias temperature instability (NBTI) for deeply scaled pMOSFETs. In this paper, we present a novel difference method to separate the time dependent fluctuation-related component from the NBTI quasi-static component in the threshold voltage shift. The extracted fluctuation-related component exhibits weak temperature and time dependences which is consistent with the characteristic of as-grown defect-induced trapping and detrapping while the quasi-static component presents electrical behaviors of generated-defect-induced NBTI degradation. On the basis of these results, a composite NBTI model is constructed and lifetime projection is derived for the small pMOSFETs.

Characterization and Modeling of NBTI in Nanoscale UltraThin Body UltraThin Box FD-SOI MOSFETs

The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

Analytical parameter extraction for NBTI reaction diffusion and trapping/detrapping models

Accurate parameters of negative bias temperature instability (NBTI) model are essential to predict the circuit lifetime during circuit design. This paper presents the extraction methods of NBTI model parameters for the NBTI reaction-diffusion (R-D) and trapping/detrapping (T/D) models. The R-D model parameters extraction mainly includes two steps: linear approximation and optimized extraction. In the first step, the term of ΔVth1/2n is described as approximately linear with t0.5 after the coordinate system conversion, where ΔVth is the degradation in threshold voltage and t is elapsing time. Then, the model parameters can be roughly calculated. In the second, an objective function of the genetic algorithm (GA) has been built up and its constraints can be determined by referring the values gotten from the first step. After solving the function, a set of accurate parameters of the NBTI model can be achieved. Similarly, the T/D model parameters extraction involves the curves fitting and further optimization based on the GA. Both the R-D and T-D extraction methods have been validated using a 40-nm CMOS process, and it is easy to implement the extraction procedures in a program extractor.

Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28nm HfO2-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.

A lifetime-aware analog circuit sizing tool

Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.

Distribution characteristic of p-channel metal-oxide-semiconductor negative bias temperature instability effect under process variations

Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system

In the nanoscale regime, the aggressive scaling of devices is affected by several severe reliability issues, including negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD). Generally, the mathematical models of NBTI and GOBD are derived from device level test structures with accelerated tests. However, although both models are highly dependent on temperature and the gate voltage and both mechanisms are based on the probability of trap generation in the oxide layer, each model has a different impact on circuit performances. In this paper, we use a physical probability model of trap generation for both mechanisms. We first simulate the impact on circuits using process models involving threshold voltage shifts and gate oxide leakage currents for NBTI and GOBD, respectively. Then, we find a relationship between the model parameters and power/ground signal degradation. We find the stress conditions that make each of the two mechanisms dominant in the power/ground signal. We calibrate the NBTI and GOBD model parameters of each chip to experimental results. Hence, it becomes possible to identify chips that are more or less vulnerable to NBTI and GOBD.

Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators

A feasible computational framework that enables improved predictability of NBTI degradation within commercially available tools is discussed. The NBTI model is used for real-time circuit operation where recovery is present. The complementary nature of implementation is readily incorporated into existing model extraction and verification tools. The method provides significantly enhanced accuracy in simulations when compared to circuit data, yet retains practicality and flexibility.

Effects of gate stack structural and process defectivity on high-k dielectric dependence of NBTI reliability in 32 nm technology node PMOSFETs.

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

Workload assignment considering NBTI degradation in multicore systems

With continuously shrinking technology, reliability issues such as Negative Bias Temperature Instability (NBTI) has resulted in considerable degradation of device performance, and eventually the short mean-time-to-failure (MTTF) of the whole multicore system. This article proposes a new workload balancing scheme based on device-level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. Starting with NBTI-induced threshold voltage degradation, we define a concept of Capacity Rate (CR) as an indication of one core's ability to accept workload. Capacity rate captures core's performance variability in terms of delay and power metrics under the impact of NBTI aging. The proposed workload balancing framework employs the capacity rates as workload constraints, applies a Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on a 64-core system show that by allowing a small part of the cores to relax over a short time period, the proposed methodology improves multicore system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).