Negative Bias Temperature Instability Characteristics Research Articles

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574056 and 61204038), the Natural Science Funds of Shanghai, China (Grant No. 14ZR1412000), the Fund from the Science and Technology Commission of Shanghai Municipality (Grant No. 14DZ2260800), and Shanghai Sailing Program (Grant No. 17YF1404700).

The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps ( in gate insulator, generated traps ( in bulk insulator, and interface trap generation (. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal–oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction–diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.

Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

Experimental Study on NBTI Degradation Behaviors in Si pMOSFETs Under Compressive and Tensile Strains

In this letter, we experimentally investigated the effects of four types of strains, uniaxial tensile strain, uniaxial compressive strain, biaxial tensile strain, and biaxial compressive strain, on the negative bias temperature instability (NBTI) degradation behaviors of Si pMOSFETs. The strains were applied using a wafer bending system to avoid processing effects on the NBTI characteristics as a result of strain engineering. We confirm experimentally, for the first time, that both uniaxial and biaxial compressive strains are advantageous in terms of the NBTI improvement in Si pMOSFETs. However, the NBTI reliability was degraded under both uniaxial and biaxial tensile strains. These results could not be explained by considering only the gate leakage current change due to the strain. The strain-induced modulation of the interaction between the carriers and Si-H bonds at the interface must also be considered.

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds=−0.1V and gate channel length L=1μm), and seems to be dominated by a minimally required critical length (L=0.2μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.

Germanium PMOSFETs with Low-Temperature Si2H6 Passivation Featuring High Hole Mobility and Superior Negative Bias Temperature Instability

We investigate negative bias temperature instability (NBTI) on high performance Ge p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with low-temperature Si2H6 passivation. The Ge pMOSFETs exhibit an effective hole mobility of 311 cm2/V·s at an inversion charge density of 2.5 × 1012 cm−2. NBTI characterization is performed to investigate the linear transconductance (GM,lin) degradation and threshold voltage shift (ΔVTH) under NBT stress. Ge pMOSFETs with a 10 yr lifetime at an operating voltage of −0.72V are demonstrated. The impact of the Si2H6 passivation temperature is studied. As the passivation temperature increases from 350°C to 550°C, the degradation of NBTI characteristics, e.g., GM,lin loss, ΔVTH and an operating voltage for a lifetime of 10 yr, is observed.

Refined NBTI characterization of arbitrarily stressed PMOS devices at ultra-low and unique temperatures

We reexamine degradation and recovery dynamics in the negative bias temperature instability (NBTI) of p-channel metal oxide semiconductor field effect transistors (PMOSFETs) by making use of the recently developed in situ polyheater technique. The capability of switching the device temperature extremely fast and almost arbitrarily allows for measuring differently stressed devices directly after the termination of stress at a unique and much lower characterization temperature (e.g. −60°C). This procedure (‘degradation quenching’) is a powerful extension of the conventional measure–stress–measure (MSM) technique and provides a cleaner way for comparing threshold voltage shifts and charge pumping (CP) currents of arbitrarily stressed devices. We find that increasing the stress bias predominantly activates a larger number of defects with similar (short) recovery time constants causing steeper threshold voltage recovery transients after the termination of stress. Increasing the stress temperature has a very similar effect on the threshold voltage shift as increasing the stress time. In both cases, defects with larger recovery time constants are activated while the number of defects with short recovery time constants remains essentially the same. A comparison of VTH shift and CP data suggests that the total threshold voltage shift is due to at least two fundamentally different types of defects, one being readily recoverable and uncorrelated to the CP current while the other is ‘quasi-permanent’ and proportional to the CP current. By converting CP currents into corresponding threshold voltage shifts, we find that only about 50% of the ‘quasi-permanent’ VTH damage is due to slowly-recoverable interface states. The remaining fraction is due to another, yet undefined, positively charged defect generated at virtually the same rate.

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔVth caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and HfO2 High-k and TaN Metal Gate

We report the demonstration of Ge0.97Sn0.03 P-MOSFETs, featuring low temperature Si2H6 passivation, HfO2 high-k dielectric and TaN metal gate. Ge0.97Sn0.03 P-MOSFET with high drive current and negligible hysteresis was realized. NBTI characterization was performed to investigate the off-leakage, suthreshold swing, peak transconductance degradation and threshold voltage shift under stress. Excellent device reliability characteristics were observed.

Negative Bias Temperature Instability Characteristics and Degradation Mechanisms of pMOSFET with High-k/Metal Gate Stacks

In this work, NBTI characteristics of pMOSFET with high-k/metal gate stacks are systematic investigated and the degradation mechanisms are analyzed. The threshold voltage shift with stress time obeys power-law, but the power exponent is dependent on stress voltage, and it ranges from 0.26 to 0.16. The activation energy (Ea) under -1.4V stress is extracted as 0.24eV. Trap charging in the high-k layer dominates the NBTI degradation rather than interface state generation. The lifetime prediction prefers to power law model.

Threshold Voltage and Mobility Extraction of NBTI Degradation of Poly-Si Thin-Film Transistors

The conventional continuous scan and Delay-ID, lin methods of negative bias temperature instability characterization are not applicable for polycrystalline silicon thin-film transistors due to significant recovery effect and mobility degradation, respectively. An improved on-the-fly (OTF) method is proposed to simultaneously extract the threshold voltage shift and mobility degradation. In addition, the improved OTF method is more accurate than the continuous scan due to less recovery effect. The exponents of reaction-diffusion mechanism can be clearly determined using the new method.

“Non-Hydrogen-Transport” Characteristics of Dynamic Negative-Bias Temperature Instability

It has been proposed that negative-bias temperature instability (NBTI) is driven by interface-state generation, rate limited by hydrogen <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">transport</i> . In this letter, we examine dynamic NBTI characteristics and present evidence which does not conform to a hydrogen-transport model. It is observed that the amount of recovery of the threshold voltage shift |Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> | remains constant, independent of the number of stress/recovery (SR) cycles. This behavior is inconsistent with the hydrogen-transport model, which stipulates that the amount of |Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> | recovery should decrease with increase in the number of SR cycles. Results show that dynamic NBTI is made up of a symmetric "switching hole-trap" mechanism superimposed on a background of relatively permanent deep-level hole trap and interface-state generation.

Pulse stress frequency dependence of negative bias temperature instability in SiON gate transistors

Dependence of negative bias temperature instability (NBTI) on the frequency of the pulsed stress applied on p-channel transistors with plasma nitrided SiON gate dielectrics is studied. The threshold voltage shift (ΔVth) decrease is observed with increase in frequency. The fractional relaxation is found to be more remarkable after a pulse stress with higher frequency. A phenomenological model based on the dispersive transport of hydrogen in the gate dielectrics is proposed to explain the pulse based NBTI characteristics. The frequency dependence of NBTI is attributed to the existence of deep level hydrogen traps in the gate dielectrics. The model predicts reduced frequency dependence in the ultrahigh frequency range. The results and discussion also confirm the overall correctness of the dispersive transport framework in interpreting the NBTI mechanisms.

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO 2 gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, Δ V TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO 2 interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO 2 interface ( P b centers) and its vicinity ( E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I D − V G (Δ V TH) techniques, however, suggests that Δ V TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO 2/SiO 2 gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO 2 and high-k gate stacks suggesting a common mechanism of the interface degradation.

Dynamic NBTI characteristics of PMOSFETs with PE-SiN capping

Negative-bias-temperature instability (NBTI) characteristics of strained p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) under dynamic and AC stressing were investigated in this work. The compressive strain in the channel was deliberately induced by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer in this study. It was found that the capping would degrade the NBTI characteristics, although the degradation is relieved when the stress frequency increases. The aggravated NBTI behaviors are ascribed to the higher amount of hydrogen incorporation during SiN deposition.

A Generalized Reaction–Diffusion Model With Explicit H– $\hbox{H}_{2}$ Dynamics for Negative-Bias Temperature-Instability (NBTI) Degradation

In this paper, negative-bias temperature-instability (NBTI) modeling, based on a generalized reaction-diffusion framework, is presented. Unlike the previous models, the release of atomic hydrogen from the Si-H bonds at the Si/oxide interface and its subsequent conversion into molecular H2 are considered without the (unphysical) assumption of instantaneous transition. The conversion reactions are handled explicitly with finite transition time and numerical solutions that contain both H and H 2 dynamics are obtained. The conversion reactions result in a distinct time behavior which cannot be predicted from either H- or H2-only simulations. The results are then explained analytically. The implications of hydrogen conversion dynamics on saturation of NBTI characteristics and device lifetimes are also discussed

Negative bias temperature instability characteristics of strained SiGe pMOSFETs

Investigation of the negative bias temperature instability (NBTI) mechanism of a strained Si0.7Ge0.3 pMOSFET with 30 nm tetraetho oxysilane (TEOS) oxide is presented. Because the carriers are confined in the buried SiGe channel, less threshold voltage shift and smaller drain current degradation are found in a strained SiGe pMOSFET compared to the Si control counterpart. Further, data of thermal active energy (Ea) are in agreement with the reaction-diffusion model. Our findings reveal that the strained Si0.7Ge0.3 pMOSFET has improved electrical properties and NBTI immunity because of less drain current degradation, less threshold voltage shift and longer lifetime.

A Simple Negative Bias Temperature Instability Characterization Methodology to Minimize the Immediate Recovery Effect during Measurement

Negative bias temperature instability (NBTI) degradation of p-channel metal–oxide–semiconductor field effect transistors ( p-MOSFETs) is significantly underestimated by using the conventional characterization techniques due to a severe NBTI recovery during the measurements. In this work, a simple characterization method based on the single-point measurement of the saturated drain current is proposed to minimize the unwanted recovery effect. This method is accurate as is proven by a carefully-designed experiment. With this new proposed method, the measurement time is reduced to tens of milliseconds. This method gives a closer-to-real threshold voltage shift, and yields a more reliable power-law factor and thus a more realistic NBTI picture.

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.

Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

We investigated the negative bias temperature instability (NBTI) of bulk fin field effect transistor (FinFET) for the first time. Because bulk FinFET has a body terminal, it is more flexible in studying NBTI characteristics than a silicon on insulator (SOI) FinFET (no body terminal). The dependence of NBTI on back bias is smaller in 100 nm bulk FinFET with a fin width of 30 nm than in conventional planar channel devices. The bulk FinFET with the side surface orientation of (100) showed better NBTI than the device with the orientation of (110). The fin width variation has little impact on the NBTI of bulk FinFET. Moreover, the device with longer channel showed less degradation.