Negative Bias Temperature Instability Aging Research Articles

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity.

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor’s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor.

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

Aging-Aware Task Scheduling for Mesh-Based Network-on-Chips Under Aging Effect

The aging effect induced by negative bias temperature instability (NBTI) is a universal issue existing in electronic equipments. NBTI aging effect can increase the path delay of network-on-chip (NoC) device, resulting in the decreased frequency of processor core and in turn its performance degradation. Under this circumstance, aging-aware task scheduling becomes a complex and challenging problem in advanced multicore systems. This paper presents an aging-aware scheduling method that incorporates NBTI aging effect into the task scheduling framework for mesh-based NoCs. The proposed method relies on a NBTI aging model to evaluate the degradation of core’s operating frequency to establish the task scheduling model under aging effect. Taking into account core performance degradation and the communication overheads among cores, we develop a meta-heuristic scheduling strategy based on particle swarm optimization algorithm to minimize the total execution time of all tasks. Experimental results show that the schedule obtained by the aging-aware algorithm has shorter completion time and higher throughput compared with the nonaging-aware case. On average, the makespan can be reduced by 13.55% and the throughput can be increased by 21.73% for a variety of benchmark applications.

An Aging-Aware GPU Register File Design Based on Data Redundancy

Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage $V_{th}$ over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall $V_{th}$ degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100 percent ‘0’ and ‘1’ duty cycle distributions). On average, the proposal reduces these distributions by 58 and 68 percent, respectively, which translates into $V_{th}$ degradation savings by 54 and 62 percent, respectively.

Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery

As the Internet of Things continues to spread, devices within it are given more personal information which must be protected. To provide this protection, a device known as a physical unclonable function (PUF) has been devised which takes advantage of natural variations in silicon to create a unique fingerprint which can be used for secret key generation and authentication. This fingerprint is often based upon settlement of a race condition in competing circuits which is decided by process variations and noise. In this paper, we focus on the SRAM PUF, whose fingerprint is determined by the tendency of each cell to contain a 0 or 1 after it powers on. These cells are susceptible to negative-bias temperature instability (NBTI) while storing data, which pushes their power-on tendencies away from the data they contain. We present a method by which the success rate of an SRAM to produce a correct fingerprint can be reduced to 0% in only one day using NBTI activated and accelerated by elevated voltage and temperature, followed by another method in which it can be restored to nearly 100% in less than two days using active, accelerated NBTI recovery with negative voltage and elevated temperature.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process.

Reliable Power Gating With NBTI Aging Benefits

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower $V_{\textrm {th}}$ compared with the standard STs. This can be achieved by either redesigning the STs with the identified $V_{\textrm {th}}$ value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to $21.4\times $ and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Spin transfer torque (STT) switching realized using a magnetic tunnel junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile look up tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm bulk CMOS, for the same total device area, the voltage sensing scheme offers 17% to 28% lower failure rates under combined intra-die transistor and MTJ variations, comparable delay, and 56% lower active power compared to the current sensing scheme. Moreover, we compare the reliability of the two sensing schemes under negative bias temperature instability (NBTI) of PMOS transistors. Our results indicate that the failures rates increase over time by transistor aging for both designs, and the voltage sensing scheme maintains its improved failure rate over to the current sensing scheme.

Distribution characteristic of p-channel metal-oxide-semiconductor negative bias temperature instability effect under process variations

Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes

Negative Bias Temperature Instability (NBTI) is one of the major time-dependent degradation mechanisms that impact the reliability of advanced deeply scaled CMOS technologies. NBTI can cause workload-dependent shifts on a transistor’s threshold voltage (VTH), and performance during its lifetime. This study presents a comparison of the NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. The first part of the study focuses on the NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor’s arithmetic logic unit) from the points of architectural topology and workload dependency in the planar technologies (i.e. commercial 28,45,65nm nodes), while the second part investigates the energy-delay product degradation of ring oscillators beyond the planar nodes (i.e. research-grade 14,10,7nm FinFET technology nodes for several FET channel materials, e.g. Si, SiGe, Ge, InGaAs). Results show the tight coupling between the NBTI aging and the architectural topology, run-time workload, and technology choice.

Workload assignment considering NBTI degradation in multicore systems

With continuously shrinking technology, reliability issues such as Negative Bias Temperature Instability (NBTI) has resulted in considerable degradation of device performance, and eventually the short mean-time-to-failure (MTTF) of the whole multicore system. This article proposes a new workload balancing scheme based on device-level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. Starting with NBTI-induced threshold voltage degradation, we define a concept of Capacity Rate (CR) as an indication of one core's ability to accept workload. Capacity rate captures core's performance variability in terms of delay and power metrics under the impact of NBTI aging. The proposed workload balancing framework employs the capacity rates as workload constraints, applies a Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on a 64-core system show that by allowing a small part of the cores to relax over a short time period, the proposed methodology improves multicore system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

Reliability and variability have become big design challenges facing submicrometer high-speed applications and microprocessors designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for negative-bias temperature instability (NBTI) aging and process variations to improve the system reliability and yield. The proposed ABB circuit consists of a threshold voltage-sensing circuit and an on-chip analog controller. In this paper, post-layout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65-nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be Silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on a circuit block case study, extracted from a real microprocessor critical path. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB improves the timing yield from 74.4% to 99.7% at zero aging time and from 36.6% to 97.1% at 10 years aging time. In addition, the proposed ABB increases the total yield from 67% to 99.5% at zero aging time and from 35.9% to 97.1% at 10 years aging time.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability at both time zero and after NBTI aging increases. The time0 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability. This paper focuses on the bias temperature instability stress-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability and the trend across several technology generations. The remarkable correlation of aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.