In this work, shallow trench isolation (STI) divot depth and active area (AA) cornerrounding effects on narrow width MOSFET performance were investigated through3-dimensional (3D) TCAD simulation. More poly-silicon wrap down on thetransistor channel by deeper divot enlarges the effective channel width andimproves the gate electrostatic control over the channel. However, it is found thatthe Idsat/Ioff improvement from deep divot is only half of the effective widthincrement. By comparing the trends of extrapolated Vt at maximum Gm (Vtgm)and constant current defined Vt at sub-threshold regime (Vtsat), it is explained thatearly turn-on of the corner transistor is the main reason of the performancedescrepancy. It is demonstrated that large corner rounding can reduce the effect andhence improve Idsat/Ioff. Moreover, conformal source/drain (s/d) extension dopingshould be obtained to remove the underlap at AA side-wall.