Narrowband Low Noise Amplifier Research Articles

A Wideband CMOS LNA Using Transformer-Based Input Matching and Pole-Tuning Technique

A wideband low-noise amplifier (LNA) featuring transformer-based wideband input matching is proposed for millimeter-wave applications. By analyzing the properties of conventional series input matching networks, which were widely employed in narrowband LNAs and shunt-series matching networks for bandwidth extension, a novel input matching network possessing the merits of both was proposed. For further bandwidth extension, another peak of input impedance at a higher frequency is introduced for the proposed input matching network. Moreover, it is proved that the proposed input matching network can suppress the gate resistor noise, resulting in significant noise figure (NF) improvement of an LNA. On the other hand, the NF is further reduced by connecting a transformer between the two amplification stages, which helps suppress the noise contribution from the second stage, leading to an LNA design with NF lower than 4.5 dB over a very wide operating bandwidth. To enhance the gain bandwidth, the peak distribution, including both shunt peaking and series peaking, is discussed. By appropriately distributing these peaks, which is also known as the pole-tuning technique, a wider gain bandwidth can be obtained. To validate the proposed techniques, an LNA with two common-source (CS) stages is designed and fabricated using a 65-nm CMOS process, and the overall chip size, including all pads, is only 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The two CS stages are cascoded for dc biasing to reduce the power consumption. Experimental results show that a peak gain of 13.5 dB is achieved within a -3-dB bandwidth from 19.2 to 42.6 GHz. The measured NF is 3.1-4.5 dB, and the input 1-dB gain compression point (IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) ranges from -13.54 to -9.89 dBm in the entire gain bandwidth. The input return loss S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> is less than -10 dB over a frequency range of 16.8-38.9 GHz. Moreover, benefiting from the current-reuse technique, the power consumption of the LNA is only 6.36 mW.

Power-Efficient CMOS Cellular RF Receivers for Carrier Aggregation According to RF Front-End Configuration

This article presents power-efficient radio frequency (RF) receiver designs, particularly for advanced long-term evolution cellular applications. The two proposed single-ended receiver architectures can fully support multiple-channel RF signals in advanced carrier aggregation (CA) scenarios with maximum design flexibility depending on the RF front-end module configuration and target applications. Two different low-noise amplifier (LNA) topologies are employed in receivers to achieve different bandwidth handling capabilities and linearity requirements. The first receiver architecture utilizes narrowband LNAs with a current-reusing technique using a 28-nm low-power complementary metal-oxide-semiconductor (CMOS) technology. The proposed receiver with this single-ended narrowband LNA can handle up to three carrier components (CCs) CA. The second receiver architecture shows wideband characteristics and employs current-efficient and high linear wideband LNAs. This proposed design can support up to five CC CA and is implemented in a 14-nm Fin field-effect-transistor CMOS technology. Moreover, frequency-band switchable transformers are utilized in both designs to realize size-efficient receivers. Both proposed receivers operate at a frequency ranging from 0.6 to 2.7 GHz. The implemented narrowband and wideband receivers have conversion gains exceeding 70 and 62 dB, and achieve noise figures of less than 3.5 and 5 dB during all CA scenarios, respectively. The proposed receivers operate at a nominal supply of 1.2 and 1.0 V for 28 and 14-nm CMOS technologies, respectively.

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

A Survey on Ultra Wide Band and Narrow Band Low Noise Amplifiers for Wireless Transceivers

A Survey on Ultra Wide Band and Narrow Band Low Noise Amplifiers for Wireless Transceivers

A low noise stable radiometer front-end for passive microwave tissue thermometry

ABSTRACTA low noise, high gain, stable radiometer front-end is presented for non-invasive tissue thermometry using custom designed narrow band low noise amplifiers (LNAs) and band pass filter (BPF) with 1.3 GHz centre frequency and − 20 dB pass band of 332 MHz. The fabricated LNAs have >15 dB gain, unconditional gain stability and noise figure (NF) < 1.45 dB in the pass band. The maximum insertion loss of the BPF is <1 dB over 1.2–1.4 GHz with 50 dB suppression in the surrounding communication bands. The cascaded radiometer front-end has measured gain of 45–50 dB, NF < 1.75 dB in the pass band and > 30 dB suppression in the adjacent personal communication bands. The Allan deviation of the total power radiometer indicates long term system stability and presence of Gaussian thermal noise for integration time, . Radiometer measurements of a matched load at room temperature for indicate acceptably low influence of external electromagnetic interference (EMI) and system noise equivalent temperature of 145 K. The brightness temperature measured by the total power radiometer using a resonant slot antenna demonstrates the ability to detect a 0.3°C change in the test load temperature with better than 0.1°C accuracy.

Design of high performance narrowband low noise amplifier using on-chip orthogonal series stacked differential fractal inductor for 5G applications

Inductors play a crucial role in the design of radio frequency integrated circuits (RFICs) and they typically consume a considerably large area and have a low-quality factor at high frequencies. The employment of fractal structure in on-chip inductors helps in improving the quality factor and also reduces the overall area besides improving the inductance value. In this paper, an orthogonal series stacked differential fractal inductor is proposed and the same is used to design a low noise amplifier (LNA) for 5G band (27--30 GHz) applications. The proposed inductor is fabricated on a multilayer printed circuit board and the measurement results demonstrate twice the enhancement in inductance, 56 % improvement in quality factor, and 33 % reduction in series resistance when compared to the conventional series stacked fractal inductor for the equivalent on-chip area. The LNA using cascode topology with inductive source degeneration is designed and simulated at a center frequency of 28 GHz in 90 nm CMOS technology using the tool Advanced Design System. The inductors in the LNA are replaced with the proposed on-chip inductor for different layers, which contributes to high gain, better input matching, and low noise figure compared to the state-of-the-art LNAs.

Heavy ion impact on narrow band cascoded low noise amplifier

The impact of heavy ion strike on a cascoded narrow band low noise amplifier (LNA) is analyzed in this work using numerical device simulations. The impact is analyzed in the time as well as the frequency domains. The LNA uses 45 nm channel length MOSFETs. The most vulnerable portion of the most vulnerable device is chosen for irradiation study. As a part of the study, the influence of the source degeneration inductor of the LNA on single event impact is analyzed. The collected charge due to single event transient current reflects the severity of the radiation strike, and the same is taken as the performance metric in the study. It was found that the larger value of source degeneration inductor mitigates the SET impact but it trades off with the gain and noise figure of the LNA.

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.

High-gain sub-decibel noise figure low noise amplifier for atmospheric radar

This article presents the design of a compact and low-cost single-stage narrow band low-noise amplifier (LNA) for atmospheric radar application. Active feedback technique is employed to improve linearity without affecting the noise figure and gain. The source-degenerated inductor topology is used along with the cascaded transistors to achieve stability with maximum gain and minimum noise figure simultaneously. High-pass input and output matching circuits are used to improve input and output return losses. The amplifier was implemented on a low-loss substrate RT/duroid with pseudomorphic high electron mobility transistor (pHEMT) technology at 1.3 GHz. The measured results of LNA exhibit a gain of 28 dB and noise figure of 0.39 dB. The input and output return losses are <10.8 dB and third-order input intercept point is 33 dBm. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1618–1622, 2016

A 65 nm CMOS resistive feedback noise canceling LNA with tunable bandpass from 4.6 to 5.8 GHz

Two low-noise amplifiers (LNA) with single ended input and differential output (balun) for multi-standard wireless receivers up to 6 GHz are presented. The proposed LNA's are based on resistive-feedback concept, which enables wide-band input impedance matching and gain. A measured test structure of the first LNA shows a wide-band gain of 22 dB in a band of 0.2---5 GHz. Due to different noise cancellation techniques, the proposed LNA achieves a superior low noise figure (NF) of 1.7 dB at 2.5 GHZ. The IIP3 linearity and 1 dB compression point of the LNA are about ?4 and ?16.1 dBm at 2 GHz respectively. To relax external RF filters and LNA linearity requirements, a second LNA version with an on-chip LC bandpass load enabling a tunable center frequency from 4.6 to 5.8 GHz is presented. The LNA achieves a measured gain up to 30 dB and an IIP3 linearity between ?6.5 and ?10.3 dBm. The NF reaches a low value of 1.6 dB in the band of interest. Both LNA circuits are implemented in 65 nm CMOS technology with an active chip area of 112 × 78 and 154 × 197 μm2 respectively. Therefore the proposed LNA structures are a cost-effective alternative to source-degeneration based narrow-band LNA's with comparable performance. Since wide-band input impedance matching is employed, the LNA's can be used in re-configurable multi-standard wireless low-cost applications.

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Low-noise amplifier with narrow-band and wide-band input impedance matching design

A low-noise amplifier (LNA) with cascode structure and shunt-peaking load is presented in this article. Both Narrow-band input impedance and wide-band input impedance LNAs were implemented in 0.18 μm CMOS process. Maximum power gain of the narrow-band input impedance LNA is 19.3 dB; maximum power gain of the wide-band input impedance LNA is 15.3 dB. Minimum noise figure of the narrow-band input impedance LNA is 3.1 dB; minimum noise figure of the wide-band input impedance LNA is 3.0 dB. Power consumptions including buffers are 24.5 and 25.6 mW, respectively.

A Low Power 5.8GHz Fully Integrated CMOS LNA for Wireless Applications

A low power 5.8 GHz fully integrated CMOS low noise amplifier (LNA) with on chip spiral inductors for wireless applications is designed based on TSMC 0.18 µm technology in this paper. The cascode structure and power-constrained simultaneous noise and input matching technique are adopted to achieve low noise, low power and high gain characteristics. The proposed LNA exhibit a state of the art performance consuming only 6.4mW from a 1.8V power supply. The simulation results show that it has a noise figure (NF) only 0.972 dB, which is perfectly close to NFmin while maintaining the other performances. The proposed LNA also has an input 1-dB compression point (IP1dB) of -21.22 dBm, a power gain of 17.04 dB, and good input and output reflection coefficients, which indicate that the proposed LNA topology is very suitable for the implementation of narrowband LNAs in 802.11a wireless applications.

A 3.8-mW 3.5–4-GHz Regenerative FM-UWB Receiver With Enhanced Linearity by Utilizing a Wideband LNA and Dual Bandpass Filters

A low-power regenerative frequency-modulated ultra-wideband (FM-UWB) receiver with wideband signal reception and linear FM-AM conversion is implemented in 65-nm CMOS for short-range communication systems. Different from the conventional regenerative FM-UWB receiver having the narrowband low-noise amplifier (LNA), the proposed receiver employs a wideband LNA and dual bandpass filters (BPFs) to improve the robustness against narrowband interference and frequency shift-keying demodulation with a relaxed Q requirement of the BPF. A 3.5-4-GHz FM-UWB receiver consisting of a stacked LNA, dual BPFs, two envelop detectors, and a subtractor successfully performs FM demodulation through wireless transmission from a 100-kb/s FM-UWB transmitter, consuming the total power of 3.8 mW.

Sensitivity of narrow- and wideband LNA performance to individual transistor model parameters

Although it is desirable for a transistor model to be as accurate as possible, the extraction of model parameters from fabricated transistors is a time-consuming and often costly process. An investigation of the sensitivity of low-noise amplifier (LNA) performance characteristics to individual parameters of the physics-based standard HBT model HICUM/L2 was, therefore, done to gain a preliminary insight into the most important parameters for transistors used in actual circuits. This can potentially allow less strenuous accuracy requirements on some parameters which would ease the extraction process. Both a narrow- and wideband LNA configuration were investigated. It was found that the series resistance parameters have a large impact on LNA gain, S 11 and noise figure performance in both cases. Since the narrow-band LNA relied heavily on the transistor characteristics to provide a proper matching, it was also very sensitive to changes in the parameters used in modelling the high-frequency current gain and depletion capacitances of the transistor.

Figure of merit for narrowband, wideband and multiband LNAs

In software defined radio, the same radio front end is used to accommodate different wireless standards operating in different frequency bands. The use of wideband or multiband low noise amplifiers (LNAs) is mandatory in such situations. There are several figures of merit (FoMs) proposed for narrowband LNAs. These FoMs are modified for wideband/multiband LNAs just by the inclusion of 3 dB bandwidth, and designers tend to use the one that favours their own design. In this article, a review of the existing FoMs for narrowband LNAs is presented. Based on this analysis, we propose two different FoMs for fair comparison of improvement in LNA parameters due to complementary metal oxide semiconductor (CMOS) technology advancement and circuit optimisation (irrespective of transistor technology), separately. The empirical technology scaling factor for gain, noise figure (NF), f T and linearity is used to differentiate between these FoMs for different types of LNAs.

A 0.7 V 850 μW CMOS LNA for UHF RFID reader

The design of a narrow-band cascoded CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this work the finite gds (= 1/r0) effect has been considered to improve the nanometric design, achieving simultaneous impedance and minimum Fmin noise matching at a very low power drain of 850 μW from a 0.7-V supply voltage. The LNA was fabricated using the IBM 130 nm CMOS process delivering a power gain (S21) of ≈12 dB, a reverse isolation (S12) of ≈−34 dB, and an input power reflection (S11@866 MHz) of ≈−12 dB. It had a minimum pass-band NF of around 2.2 dB and a 3rd order input referred intercept point (IIP3) of ≈−9.5 dBm. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2780–2782, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25600

A 12 dB 0.7 V W CMOS LNA for 866 MHz UHF RFID Reader

The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finite effect has been considered to improve the nanometric design, achieving simultaneous impedance and minimum noise matching at a very low power drain of 850 from a 0.7 V supply voltage. The LNA was fabricated using the IBM 130 nm CMOS process delivering a forward power gain () of , a reverse isolation () of , an output power reflection ( @866 MHz) of , and an input power reflection ( @866 MHz) of . It had a minimum pass-band of around 2.2 dB and a third-order input referred intercept point (IIP3) of .

A 0.13-.MU.m CMOS Ultra-Wideband Low-Noise Amplifier with High Impedance n-Well Terminals

A resistive feedback-based ultra-wideband (UWB) CMOS low noise amplifier (LNA) has been proposed. The resistive feedback technique provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrow band LNA input. Compared to the previously reported topology, all passive elements like inductor have been fully integrated in this work. In addition, to improve RF performances, all n-well terminals of the triple-well transistors used for the proposed LNA are connected to the supply voltage through a high value of resistor. The proposed UWB amplifier is implemented in 0.13 ㎛ CMOS technology for a 3 ~ 5 ㎓ frequency band. Measurements show a power gain of + 10 ㏈ gain over 6 ㎓, a minimum (maximum) NF of 2.3 ㏈ (3.8 ㏈), better than -8 ㏈ of input matching, and an input IP3 of ?4 ㏈m, while consuming only 7.5 ㎽ from a 1.5 V supply voltage.

Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband Applications

Extremely compact resistive-feedback CMOS low-noise amplifiers (LNAs) are presented as a cost-effective alternative to multiple narrowband LNAs using high-Q inductors for multiband wireless applications. Limited linearity and high power consumption of the inductorless resistive-feedback LNAs are analyzed and circuit techniques are proposed to solve these issues. A 12-mW resistive-feedback LNA, based on current-reuse transconductance boosting is presented with a gain of 21 dB and a noise figure (NF) of 2.6 dB at 5 GHz. The LNA achieves an output third-order intercept point (IP3) of 12.3 dBm at 5 GHz by reducing loop-gain rolloff and by improving linearity of individual stages. The active die area of the LNA is only 0.012 mm2. A 9.2-mW tuned resistive-feedback LNA utilizing a single compact low-Q on-chip inductor is presented, showing an improved tradeoff between performance, power consumption, and die area. At 5.5 GHz, the fully integrated LNA achieves a measured gain of 24 dB, an NF of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2-V supply and has a 3-dB bandwidth of 3.94 GHz (4.04-7.98 GHz). The LNA occupies a die area of 0.022 mm2. Both LNAs are implemented in a 90-nm CMOS process and do not require any costly RF enhancement options.