Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

Abstract

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.