Nanowire Thin-film Transistors Research Articles

Cd0.2Zn0.8O nanowire thin film transistor for low kickback high-speed AMLCD circuit applications

This paper reports the Cd0.2Zn0.8O channel cylindrical gate-all-around nanowire thin-film transistor (CY-GAA-NWTFT) for high-speed active-matrix liquid crystal display (AMLCD) pixel circuit with minimal kickback voltage. The AC/DC, analog, and energy efficiency of this device are investigated against the variation in lateral (channel length) as well as vertical dimension (oxide thickness) using technology computer aided design (TCAD) device simulation environment. Further, the behavior of CY-GAA-TFT is crosschecked by implementing it on resistive load digital inverter circuit followed by transient analysis to calculate delay of the inverter circuit. Moreover, static analysis has been also performed to evaluate its voltage transfer curve (VTC) to derive its noise margin and voltage gain. The execution of the proposed CY-GAA-NWT device on AMLCD pixel circuit indicates tremendous improvement in performance in terms of high-speed applications and low kickback voltage.

Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data

The randomly fluctuating trap efficiency of taper-etched nanowire thin-film transistors was investigated by measuring a very large statistical ensemble of three-dimensional NAND flash memory cells. We made trapping in n-bit multi-level cells using incremental step pulse programming and observed the widening of the threshold voltage distribution caused by abnormal program cells. Further, we classified the components that broaden the threshold voltage distribution in both chip- and wafer-level measurements to analyze behaviors of the randomly fluctuating abnormal program cell. The variations in reading and programming operations are difficult to separate because they act simultaneously in the data reading and writing operations. For each pulse of the programming, the variations occur in reading for verification, in programming itself, and in reading after program completion. To analyze the inseparable variation, we used a method to extract only the intrinsic over-programming by removing variations in the read operation from the entire abnormal program cell. Using this extraction method, we could distinguish between the simultaneous read variation and over-programming. In particular, the unpredictable effect of the three-dimensional structure, such as the irregular shape and different radius due to the tapered channel hole profile from the nonideal etching process, was calculated and verified using experimental data. We quantitatively analyzed the experimental data one by one for each cell within the entire distribution, and each pulse of dozens in the programming scheme. This analysis provides quantitative information on the variations in charge-trapping efficiency and the threshold voltage distribution width by irregular-shaped tunneling layers.

Improvements of Electrical Characteristics in Poly-Si Nanowires Thin-Film Transistors with External Connection of a BiFeO3 Capacitor.

By a sol–gel method, a BiFeO3 (BFO) capacitor is fabricated and connected with the control thin film transistor (TFT). Compared with a control thin-film transistor, the proposed BFO TFT achieves 56% drive current enhancement and 7–28% subthreshold swing (SS) reduction. Moreover, the effect of the proposed BiFeO3 capacitor on IDS-VGS hysteresis in the BFO TFT is 0.1–0.2 V. Because dVint/dVGS > 1 is obtained at a wide range of VGS, it reveals that the incomplete dipole flipping is a major mechanism to obtain improved SS and a small hysteresis effect in the BFO TFT. Experimental results indicate that sol-gel BFO TFT is a potential candidate for digital application.

Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric.

For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm2/Vs and on/off ratio of ~106, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm2/Vs and an on/off ratio of >105. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs.

High Performance Si Nanowire TFTs With Ultrahigh on/off Current Ratio and Steep Subthreshold Swing

Seeking high drive current, low leakage and swift switching is critical in developing high performance thin film transistors (TFTs) for portable and flexible displays. In this work, we report on the fabrication of high performance TFTs, based on orderly in-plane silicon nanowire (SiNW) array grown at 350 °C, which demonstrate a high ON/ OFF current ratio of $5{\times }{{10}}^{{8}}$ , with a steep subthreshold swing (SS) of 100 mV/dec and a hole mobility of 80 cm2/Vs. The high on current of ${10}~{\mu } {A}$ has been obtained under ${{{0.75} }}{V}$ bias for a channel consisting of only 10 parallel SiNWs, with a mean diameter of ${\sim 66}{\textit {nm}}$ and channel length of ${{2}}~{\mu } {m}$ . In addition, SiNW inverters are also constructed, operating at a drive voltage of 2 V and achieving a gain above 11. These results highlight the geometric advantage of the SiNW TFTs in constructing a new generation of high performance, low cost and scalable display logics and flexible electronics.

Nanowire Electronics: From Nanoscale to Macroscale.

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Drain Conductance Oscillations in Poly-Si Junctionless Nanowire Thin-Film Transistors

The drain conductance oscillations are simultaneously observed in the trigated and double-gated poly-Si junctionless (JL) nanowire thin-film transistors (TFTs). The strongest oscillations appear at ${V} _{\text {GS}}$ of 1 V and $V_{\text {DS}}$ of 4–5 V/6–7 V in 0.35- $\mu \text{m}$ /5- $\mu \text{m}$ poly-Si JL nanowire TFTs. To explain the drain conductance oscillations, in addition to the separated sub-bands and Coulomb blockade effect, the space-charge-potential barrier/grain boundary (GB) potential barrier in the channel and the kink effect in the output characteristics should be considered. The space-charge-potential barrier is affected by the unstable trapped electrons at GB and leads to the drain conductance oscillations. Due to the kink effect, an anomalous increase of the current in the output characteristics can enhance the conductance oscillations. Moreover, the channel of the double-gated device shows higher degree of crystallinity by solid-phase crystallization. Compared with the trigated device without solid-phase crystallization, less GB potential barriers in the channel of the double-gated device lead to a higher mobility in the channel, and these electrons can easily destroy the stability of the trapped electrons at the GBs, resulting in the stronger drain conductance oscillations. Therefore, the physical mechanisms are proposed to understand the drain conductance oscillations well in poly-Si JL nanowire TFTs.

Individual analysis of inter and intragrain defects in electrically characterized polycrystalline silicon nanowire TFTs by multicomponent dark-field imaging based on nanobeam electron diffraction two-dimensional mapping

We visualize the grain structures for individual nanosized thin film transistors (TFTs), which are electrically characterized, with an improved data processing technique for the dark-field image reconstruction of nanobeam electron diffraction maps. Our individual crystal analysis gives the one-to-one correspondence of TFTs with different grain boundary structures, such as random and coherent boundaries, to the characteristic degradations of ON-current and threshold voltage. Furthermore, the local crystalline uniformity inside a single grain is detected as the difference in diffraction intensity distribution.

Clean-Induced Instability of Electrical Characteristics in Poly-Si Junctionless Nanowire Transistor

A heavy doped poly-Si junctionless channel immersed in NH4OH/H2O2/H2O (SC1) solution is always unexpectedly damaged and results in an instable electrical characteristic in a proposed tri-gated nanaowire (NW) thin film transistor (TFT). A new finding indicates that a sharp nanowire profile is observed because some segregated precipitates at the poly-Si grain boundaries are etched and the dependence of the silicon etch rate on the crystal orientation/grain size also impacts the sharp corner formation in SC1 solution. Moreover, it results in damaged nanowire surface and many electron traps in subsequently deposited gate oxide. Therefore, a smaller etching amount in SC1 solution is suggested in the fabrication of a tiny poly-Si junctionless nanowire TFT.

Technology demonstration of a novel poly-Si nanowire thin film transistor**Project supported by the National Key Research and Development Program of China (Grant Nos. 2016YFA0302300 and 2016YFA0200404), the National Natural Science Foundation of China (Grant No. 61306105), the National Science and Technology Major Project of China (Grant No. 2011ZX02708-002), the Tsinghua University Initiative Scientific Research Program, China and the Tsinghua National

A simple process flow method for the fabrication of poly-Si nanowire thin film transistors (NW-TFTs) without advanced lithographic tools is introduced in this paper. The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique. The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs (used as a control). The as-demonstrated NW-TFT exhibits a small subthreshold swing (191 mV/dec), a high ON/OFF ratio (8.5 × 107), a low threshold voltage (1.12 V), a decreased OFF-state current, and a low drain-induced-barrier lowering value (70.11 mV/V). The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT. The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.

High-Performance Single-Crystal-Like Strained-Silicon Nanowire Thin-Film Transistors via Continuous-Wave Laser Crystallization

High-performance polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs) have been demonstrated via continuous-wave laser crystallization (CLC) to exhibit the low subthreshold swing of 216 mV/decade and high ON/OFF ratio of 1.6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . In addition, the thermal stress of ~800 MPa induced from the CLC process also contributed to the single-crystal-like silicon NW CLC TFTs to achieve an excellent field-effect mobility of up to 900 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> .

Poly Si Nanowire Thin Film Transistors With Vacuum Gap Design

Via a simple selective-etching technique, a poly Si nanowire (NW) thin-film transistor (TFT), accompanied with the offset region, embedded vacuum gaps, and subgate structure, has been fabricated and characterized. The embedded vacuum gaps serves as an effective thicker insulator above the offset region, thus effectively reduces OFF-state leakage current and kink effect. This is because, under gate/drain biases, the electric field at channel surface near the drain can be reduced by the vacuum gap design compared with that in the conventional NW TFT. The extension of TiN layer above vacuum gap serves as a subgate and induces an inversion layer at the offset region to maintain a high on-current. The local electrical field located at the channel spacer surface and sharp corner near the drain is much lower in proposed vacuum gap structure compared with that in conventional NW TFT. Therefore, the device reliability, such as the degradation of threshold voltage, subthreshold swing, and transconductance under dc hot-carrier stress, is obviously improved by the proposed vacuum gap structure. Therefore, this proposed NW TFT is suitable for applications in advanced system-on-panel and 3-D circuit.

Poly-Si Nanowire TFT With Raised Source/Drain and Nitride Spacer

A raised source/drain poly-Si nanowire (NW) thin film transistor (TFT), together with a nitride spacer structure, is proposed and characterized. The undoped poly-Si region under the nitride spacer is considered to be an offset region and the drain electric field is effectively reduced. In addition, the poly-gate edge covering the nitride spacer serves as a field plate and induces an inversion layer, hence it maintains a high ON-current. Therefore, this proposed NW TFT exhibits a lower OFF-state leakage current, a higher ON/OFF current ratio, and an improved kink effect.

High-Performance SLS Nanowire TFTs With Dual-Gate Structure

Gate-all-around (GAA) sequential-lateral-solidification (SLS) nanowire (NW) thin-film transistor (TFT) devices with single-gate and dual-gate structures are fabricated and characterized. Compared with planar SLS TFT, owing to only one perpendicular grain boundary in each NW channel, GAA SLS NW TFT with single-gate structure can exhibit better performances when operated at low gate/drain voltage. However, it suffers from an obvious kink effect when operated at high gate/drain voltage because of the local electrical fields located at the sharp corners in GAA structure. Via dual-gate structure design, it clearly improves the performance of TFT device, which thus has a lower leakage current, a higher ON/OFF ratio, and an improved kink effect as compared with single-gate TFTs by avoiding the perpendicular grain boundaries and reducing electrical fields near channel/drain junction regions. In addition, the device reliability, such as the threshold voltage shift, subthreshold swing, and transconductance degradation under dc hot-carrier stress, is apparently improved by the proposed structure.

Stability and Low-Frequency Noise in InAs NW Parallel-Array Thin-Film Transistors

In this letter, we present the dc characteristics, stability, and low-frequency noise (LFN) measurements, for n-type indium arsenide nanowire (NW) parallel-array thin-film transistors (TFTs) with a global back gate. These devices perform with mobilities ranging from 200-1200 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and produce a threshold voltage shift less than 0.25 V after 10 000 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</i> of stress. The resulting LFN measurements indicate that the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise can be modeled by the number fluctuation model, at low drain currents, which can provide an essential guideline for the device design considerations of NW TFTs.

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and an on/off current ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.

Characterizations of polycrystalline silicon nanowire thin-film transistors enhanced by metal-induced lateral crystallization

In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices.

Minimizing variation in the electrical characteristics of gate-all-around thin film transistors through the use of multiple-channel nanowire and NH3 plasma treatment

In this paper we describe the electrical performance of gate-all-around (GAA) thin-film transistors (TFTs) featuring poly-Si multiple-channel nanowires (NWs). To minimize the variations in the electrical characteristics of GAA NW TFTs, we compared the effects of several approach, including the use of a multiple-gate structure, the number of multiple channels, and NH3 plasma treatment. We demonstrated not only the gate configuration but also the presence of multiple channels efficiently reduced the variation in the electrical characteristics. Finally, NH3 plasma treatment of the GAA NW TFTs featuring multiple channels further decreased the electrical variations because it decreased the trap density, which modulated device performance.

Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor

Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor

A Simple and Sufficient Method to Fabricate ZnO Nanowire Thin-Film Transistors

Large-scale fabrication of ZnO nanowire (NW) based devices with a low cost process is a key issue in practical application. In this paper, we report a simple and sufficient self-assembly process to prepare highly dense, uniform ZnO NW films. In this process, the NWs are modified with the aminopropyltriethoxy silane (APTES) to form the positively charged amine-terminated layer, so they are adsorbed on negatively charged SiO2/Si substrates to form ZnO NW films by the electrostatic interaction in aqueous solution. Nanowire thin-film transistors (NW-TFTs) based on the prepared ZnO NW films are fabricated. A typical NW-TFT exhibited a current on/off ratio of 2.7×105, a transconductance of 546 nS and a field-effect mobility of 8.9 cm2/V•s. This study may pave the way toward large-scale fabrication of ZnO NW based devices with simple, sufficient and low cost process.