Abstract
Gate-all-around (GAA) sequential-lateral-solidification (SLS) nanowire (NW) thin-film transistor (TFT) devices with single-gate and dual-gate structures are fabricated and characterized. Compared with planar SLS TFT, owing to only one perpendicular grain boundary in each NW channel, GAA SLS NW TFT with single-gate structure can exhibit better performances when operated at low gate/drain voltage. However, it suffers from an obvious kink effect when operated at high gate/drain voltage because of the local electrical fields located at the sharp corners in GAA structure. Via dual-gate structure design, it clearly improves the performance of TFT device, which thus has a lower leakage current, a higher ON/OFF ratio, and an improved kink effect as compared with single-gate TFTs by avoiding the perpendicular grain boundaries and reducing electrical fields near channel/drain junction regions. In addition, the device reliability, such as the threshold voltage shift, subthreshold swing, and transconductance degradation under dc hot-carrier stress, is apparently improved by the proposed structure.
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