Poly Si Nanowire Thin Film Transistors With Vacuum Gap Design

Abstract

Via a simple selective-etching technique, a poly Si nanowire (NW) thin-film transistor (TFT), accompanied with the offset region, embedded vacuum gaps, and subgate structure, has been fabricated and characterized. The embedded vacuum gaps serves as an effective thicker insulator above the offset region, thus effectively reduces OFF-state leakage current and kink effect. This is because, under gate/drain biases, the electric field at channel surface near the drain can be reduced by the vacuum gap design compared with that in the conventional NW TFT. The extension of TiN layer above vacuum gap serves as a subgate and induces an inversion layer at the offset region to maintain a high on-current. The local electrical field located at the channel spacer surface and sharp corner near the drain is much lower in proposed vacuum gap structure compared with that in conventional NW TFT. Therefore, the device reliability, such as the degradation of threshold voltage, subthreshold swing, and transconductance under dc hot-carrier stress, is obviously improved by the proposed vacuum gap structure. Therefore, this proposed NW TFT is suitable for applications in advanced system-on-panel and 3-D circuit.