Abstract
In this letter, we present the dc characteristics, stability, and low-frequency noise (LFN) measurements, for n-type indium arsenide nanowire (NW) parallel-array thin-film transistors (TFTs) with a global back gate. These devices perform with mobilities ranging from 200-1200 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and produce a threshold voltage shift less than 0.25 V after 10 000 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</i> of stress. The resulting LFN measurements indicate that the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise can be modeled by the number fluctuation model, at low drain currents, which can provide an essential guideline for the device design considerations of NW TFTs.
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