Nanowire MOSFETs Research Articles

Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

Subthreshold swing (SS) in a silicon gate-all-around (GAA) nanowire MOSFET with zero body factor is examined from room temperature (RT) down to 4 K. A fully depleted (FD) SOI MOSFET is also evaluated. The values of SS of both transistors decrease in proportional to temperature (T) but start to saturate below 18K, similar to transistors with non-zero body factor in the literature, indicating that the body factor is not related to the SS saturation phenomena at very low temperatures.

Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length

In this work, drain current ID for 7-nm gate length dual-material (DM) cylindrical gate all around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Schrodinger's equation with Poisson’s equation. The splitting of conduction in multiple sub-bands has been considered and there is no doping in the channel region. The effect of DM gate engineering (variation of screen gate and control gate length having different work function) for SiNW channel with 2-nm radius and gate oxide (SiO2) thickness of 0.8 nm on ID have been studied. It was found that DM gate engineering reduces drain-induced barrier lowering (DIBL) but it also slightly increases sub-threshold slope (SS). This work has obtained small DIBL (~54 mV/V), small SS (~68 mV/dec), and higher IOn/IOff (~4 × 108) ratio as compared to literature concerning the inversion mode devices. The smallest DIBL is obtained when control gate length is the highest, and vice versa. With increase in control gate length, there is also increase in both IOn and IOff but IOn/IOff ratio decreases.

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

Low-Power Resistive Memory Integrated on III–V Vertical Nanowire MOSFETs on Silicon

III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore's law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to 0.01 μ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m2</sup> enabling realization of dense memory (1T1R) cross-point arrays on silicon.

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm &gt; 3 mS/μm

Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> down to L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> = 3.1 mS/μm and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> = 190 μm. This is the highest g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> demonstrated on Si. Transmission line measurement verifies a low contact resistance with R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation.

In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). In order to investigate electrical and self-heating characteristics of the proposed devices, on-current, off-current, subthreshold swing (SS), and operating temperature were examined by using 3D TCAD simulator and compared with nanowire MOSFET (NW-MOSFET). As a result, a possibility of reducing off-current and operating temperature was demonstrated by using the ONWFET with 40% GCR. Therefore, the ONWFET can save power consumption and serve as low power application such as battery-powered portable electronic devices.

Oxide Edge Trap Density Extraction in Silicon Nanowire MOSFET From Tunnel Current Noise Measurement in Gated Diode Like Arrangement

Edge traps in the gate oxide of silicon nanowire MOSFETs have been extracted from tunnel current noise measurement in a gated diode like arrangement. We have found that, low frequency noise in tunnel current results from collective response of the edge traps available within the gate oxide surrounding band-to-band generation (BTBG) region of silicon nanowire, and when the BTBG region is accessed by favorable terminal biases. From detail modeling of the phenomenon, we derived a closed form expression of the tunneling current noise power spectral density (PSD) employing which oxide edge trap density in nanowire MOSFET had been extracted through its fit with the experimental noise PSD data. We furthermore validated our model for different BTBG biases, and contrasted our result with the bulk oxide trap density in identical MOSFET, while the latter was separately estimated from the gate current noise PSD measurement. Mismatch between the oxide bulk trap and edge trap concentrations has been found, whereby actual edge trap density remains otherwise hidden from the widely employed gate current noise measurement technique. It is because, the present scheme improves the resolution of the extracted oxide edge trap concentration in surrounded gate MOSFET owing to constricted tunnel current flow near the corner of the gate which imposes selectivity on the oxide edge traps

Vertical nanowire III–V MOSFETs with improved high‐frequency gain

High-frequency performance of vertical InAs/InGaAs heterostructure nanowire MOSFETs on Si is demonstrated for the first time for a gate-last configuration. The device architecture allows highly asymmetric capacitances, which increases the power gain. A device with L g = 120 nm demonstrates f T = 120 GHz, f max = 130 GHz and maximum stable gain (MSG) = 14.4 dB at 20 GHz. These metrics demonstrate the state-of-the-art performance of vertical nanowire MOSFETs.

Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs

We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.

III–V nanowire MOSFETs with novel self-limiting Λ-ridge spacers for RF applications

We present a semi self-aligned processing scheme for III–V nanowire transistors with novel semiconductor spacers in the shape of Λ-ridges, utilising the effect of slow growth rate on {111}B facets. The addition of spacers relaxes the constraint on the perfect alignment of gate to contact areas to enable low overlap capacitances. The spacers give a field-plate effect that also helps reduce off-state and output conductance while increasing breakdown voltage. Microwave compatible devices with Lg = 32 nm showing fT = 75 GHz and fmax = 100 GHz are realized with the process, demonstrating matched performance to spacer-less devices but with relaxed scaling requirements.

SOI Schottky Barrier Nanowire MOSFET with Reduced Ambipolarity and Enhanced Electrostatic Integrity

SOI Schottky Barrier Nanowire MOSFET with Reduced Ambipolarity and Enhanced Electrostatic Integrity

Variability Effects in Nanowire and Macaroni MOSFETs—Part I: Random Dopant Fluctuations

In this article and the related Part II, we investigate variability effects on the threshold voltage of nanowire and Macaroni MOSFETs, focusing on random dopant fluctuations (RDFs) and random telegraph noise, to assess their dependences on device radius, channel length, and doping. In Part I, we address threshold voltage fluctuations induced by RDF and show that different trends emerge with respect to planar devices, being dependent on whether the conduction is bulk- or surface-dominated. Macaroni devices with thin silicon regions can improve RDF, while moving from inversion- to accumulation-mode devices results in a worsening of this parameter.

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

Effects of High-k Dielectric Materials on Electrical Performance of Double Gate and Gate-All-Around MOSFET

This paper presents the electrical behaviour of Double Gate (DG) and Gate-All-Around nanowire (GAA) MOSFET using different high permittivity (high-k) gate dielectric materials. In order to study the influence of high- k dielectric material towards DG and GAA, Atlas Silvaco TCAD tools were used to simulate the device and to determine the electrical characteristics. The high-k materials chosen in this study were Silicon Nitride (Si3N4), Aluminium Oxide (Al2O3), Zirconium Oxide (ZrO2) and Hafnium Oxide (HfO2). The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. It can be observed that HfO2 shows the best performance compared to other simulated dielectric materials for both DG and GAA MOSFET.

Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering.

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Impact of Source to Drain Tunneling on the Ballistic Performance of Si, Ge, GaSb, and GeSn Nanowire p-MOSFETs

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length (L G ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band, the k·p method was used. For each material, we simulated a set of six different transport/confinement directions, at a fixed OFF-state current (I OFF ) of 100 nA/μm and supply voltage V DD = -0.5 V to identify the direction with the highest ON-current (I ON ). For Ge, GaSb, and GeSn [001]/110/110 oriented NWFETs, with [001] being the direction of transport and 110, 110 being the directions of confinement for the nanowire, showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/110 NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Our simulation result show that with properly chosen channel transport orientation and S/D doping concentration, performance of materials with high hole mobility can be optimized to reduce the impact of SDT and provide a performance improvement over Si-channel based p-MOSFETs.

An ON-Current and Effective Drive Current Model for Nanowire MOSFETs with Random Dopant Fluctuations

We report a novel analytic model for the ON -current and effective drive current in nanowire MOSFETs considering the random dopant fluctuation effects. This model is derived from the basic drain current equation considering RDF in the channel region of the device. The model makes use of appropriate voltage relations to be applied in the oxide-interface boundary conditions, and is found to be in excellent agreement with TCAD simulations of the device considering RDF effects.

Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits

In this work, negative bias temperature instability/positive bias temperature instability (NBTI/PBTI) reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature. We have incorporated the NBTI/PBTI $\text{V}_{\mathrm{ T}}$ model in a physics-based SiNW FET Verilog-A compact model for circuit analysis. For the first time, using integrated model, we report time zero variability and BTI reliability of the core logic gates (INVERTER, NAND, and NOR) and read/write stability of 6T SRAM cell. We demonstrate that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. The benchmarking of BTI in SiNW FET with FinFET and planar devices show SiNW have higher degradation, however it can be minimized by using optimized SiNW FET configuration. Further, we show that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the read noise margin (RNM) by 15–30%, and write noise margin (WNM) improves by 5–8% for 10-Year lifetime. We find that the combined impact of time zero variability and BTI reliability degrades the mean value of circuit delay and SRAM RNM stability, however, the degradation is found to be comparable to the reported planar and FinFET data. It is also seen that different configuration increases BTI variability (~5-25% increase) which can be minimized. Using the results, we propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate SiNW FET design configuration. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis.

Hetero-Dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain

In proposed work, gate oxide engineered Schottky Barrier (SB) Hetero-Dielectric (HD) Single Metal (SM) Gate All around Nanowire MOSFET is purposed for low power digital circuitry. Proposed device has an asymmetric oxide geometry having high-k (HfxTi1-xO2) on source side and SiO2 on drain side with Schottky Source/Drain regions. Leakage currents are reduced to an order of 10−15 over 10−9 A as compared to conventional GAA MOSFET. Device is simpler in fabrication in contrast to Junctionless (JL) NWFETs due to its dopingless design. Also, it has almost negligible gate induced drain leakage (GIDL) current value. An extensive comparison is outlined between the subthreshold performance of Single metal, Dual metal Hetero-Dielectric (HD) and Gate Stack (GS) SB-SM-GAA NWFET configurations. An improvement is observed in ON to OFF-state current ratio by 68.05% and an impressive decline in drain induced barrier lowering (DIBL) by 48.15% in HD-SB-SM-GAA NWFET as compared to Gate stack structure at same physical dimensions. Further, SM device has been found to have better ION/IOFF ratio, higher transconductance, lowered DIBL and an optimum subthreshold slope as compared to DM device.