Nanowire Field-effect Transistors Research Articles

Signature of electrothermal transport in 18nm vertical junctionless gate-all-around nanowire field effect transistors

Abstract Addressing temperature hot-spots resulting from self-heating effects (SHE) poses a significant challenge in the design of emerging nanoscale transistors, such as vertical junctionless nanowire field-effect transistors (VNWFETs), due to reduced thermal conductivity. Consequently, electrothermal modeling becomes crucial for a comprehensive understanding of the underlying physical mechanisms governing carrier degradation and thermal conduction in these nanoscale devices. In this study, we present an enhanced drift-diffusion model coupled with nonlocal Guyer-Krumhansl (GK) equations to accurately capture carrier-phonon interactions and explore the electrothermal characteristics of gate-all-around (GAA) VNWFETs. Pulsed current-voltage (I–V) measurements are employed to investigate the performance of a state-of-the-art 18nm VNWFET technology. Furthermore, we report on the influences of both trapping and SHE under high-bias conditions for varying pulse widths. Our findings reveal that optimization of mobility degradation mechanisms allows for improved control over the physical behavior of carrier transport in these emerging technologies. Through careful consideration of these factors, it becomes possible to enhance the overall performance of GAA VNWFETs, particularly in mitigating temperature hot-spots and addressing challenges associated with self-heating effects.

Analysis of Different Nanostructures of ISFET Biosensors Towards Liposome Detection

Proteins are needed by all living cells for structural and functional purposes. However, some proteins such as liposome instability may result in medication leaks that could harm cells. The detection of liposomes is dependent on the complex interactions between proteins, which are necessary for both their structural integrity and functional characteristics. This emphasizes the critical role that proteins play in the precise identification and examination of liposomal structures. Ion-sensitive field-effect transistor (ISFET) biosensor has gained popularity in the clinical research field for biomolecule detection due to its high detection sensitivity, mass-production capability, and low manufacturing cost. Nanohub BioSensorLab software was used to analyze the performance of different structures of ISFET (planar, cylindrical nanowire, nanosphere and double-gate FET) by simulating the settling time and selectivity of the biosensors. As the structural dimension expands from 1D to 3D, the settling time increases by three folds at the lowest analyte concentration. The fastest settling times were achieved by planar ISFET and double-gate FET. For selectivity measurements, an enhanced selectivity was achieved by increasing the concentration of the target molecule and decreasing the concentration of the parasitic molecule. A higher selectivity is determined by the higher Signal-to-Noise Ratio (SNR) value. The SNR increased linearly corresponds to the increase in the concentration of the target molecule as well as the decrease in the parasitic molecule’s concentration. The parasitic molecule's size increase of 1 nm causes a rise in SNR of 5.00×103.

Correction: Improved analog and AC performance for high frequency linearity based applications using gate-stack dual metal (DM) nanowire (NW) FET (4 H-SiC)

Correction: Improved analog and AC performance for high frequency linearity based applications using gate-stack dual metal (DM) nanowire (NW) FET (4 H-SiC)

A proposal and simulation analysis for a novel architecture of gate-all-around polycrystalline silicon nanowire field effect transistor

A proposal for a novel gate-all-around (GAA) polycrystalline silicon nanowire (poly-SiNW) field effect transistor (FET) is presented and discussed in this paper. The device architecture is based on the realization of poly-SiNW in a V-shaped cavity obtained by tetra methyl ammonium hydroxide (TMAH) etch of monocrystalline silicon (100). The device’s behavior is simulated using Silvaco commercial software, including the density of states (DOS) model described by the double exponential distribution of acceptor trap density within the gap. The electric field, potential, and free electron concentration are analyzed in different nanowire regions to investigate the device's performance. The results show good performance despite the high density of deep states in poly-SiNW. This can be explained by the strong electric field caused by the corner effect in the nanowire, which favors the ionization of the acceptor traps and increases the free electron concentration.

Peculiarities of the SCLC Effect in Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors

AbstractHigh‐quality liquid gate‐all‐around (LGAA) silicon nanowire (NW) field‐effect transistor (FET) biosensors are fabricated and studied their properties in 1 mm phosphate‐buffered saline solution with pH = 7.4 using transport and noise spectroscopy. At small VDS, the conventional current behavior of FET with a linear dependence on voltage is registered in the output current‐voltage (I‐VM) characteristics with M = 1. At drain‐source voltage VDS > 0.6 V, the I‐V characteristics with stronger power M are revealed. It is shown that the current in LGAA NW FETs follows current proportional to voltage in power M = 4 dependence on small liquid gate voltages. Transport and noise spectroscopy analyses demonstrate that the obtained results are associated with the space‐charge‐limited current (SCLC) effect. Moreover, a strong two‐level random telegraph signal (RTS) is found in the region corresponding to SCLC at VDS values exceeding 0.6 V. The RTS related to single trap phenomena results in a well‐resolved Lorentzian component of noise spectra. The results demonstrate that the SCLC and two‐level RTS phenomenon are correlated effects. They should be taken into account during the development of single‐trap‐based devices, including biosensors.

Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs).

In this study, we investigated the influence of quasi-one-dimensional (Quasi-1D) characteristics on the source and drain contact resistances within vertical nanowire (NW) field-effect transistors (FETs) of diminutive diameter. The top contact of the NW is segregated into two distinct regions: the first encompassing the upper surface, designated as the axial contact, and the second encircling the side surface, known as the radial contact, which is formed during the top-contact metal deposition process. Quantum confinement effects, prominent within Quasi-1D NWs, exert significant constraints on radial transport, consequently inducing a noticeable impact on contact resistance. Notably, in the radial direction, electron tunneling occurs only through quantized, discrete energy levels. Conversely, along the axial direction, electron tunneling freely traverses continuous energy levels. In a meticulous numerical analysis, these disparities in transport mechanisms unveiled that NWs with diameters below 30 nm exhibit a markedly higher radial contact resistance compared to their axial counterparts. Furthermore, an increase in the overlap length (less than 5 nm) contributes to a modest reduction in radial resistance; however, it remains consistently higher than the axial contact resistance.

Comparison of SiGeC/SiGe/SiC–Si heterojunction based vertical nanowire FET using non equilibrium Green's function

Advancement in FET technology has forced researchers to seek alternate semiconductor devices and materials. TFETs, junctionless FETs, and nanowires are a few examples of modern FETs, whereas Si alloys, graphene, and TMDC are a few materials that have shown promising behaviour to replace Si in the future. In this work, SiGeC/SiGe/SiC–Si based vertical heterostructure nanowires have been investigated. Due to the nanoscale dimensions of the FET and to incorporate the quantum effects along with Schrodinger-Poisson equations, non-equilibrium Green's function has been used as a principle simulator. For simulation, Ge/Carbon mole concentration of 0.25 and 0.01, respectively is used. To thoroughly investigate the effect of variation in doping profile and temperature range, simulated heterojunction nanowire showed that SiGeC-based nanowire result in a better ION/IOFF ratio as compared to SiGe and SiC-based heterojunction nanowire.

Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity

MOSFETs have been used in integrated circuits for a long time. These were replaced by FinFET’s in 2011. But for short-channel devices, FinFET’s have low performance due to various effects like velocity saturation, hot carrier effect, drain-induced barrier lowering, channel length modulation, fringing field effect, sub-threshold conduction, threshold voltage roll-off, etc. Gate All Around FET (GAA FET) is the best device that will replace the FinFET’s. Therefore, during the fabrication process, it is crucial to investigate the effects of process variations caused by changes in device dimensions. This research discusses the performance of the proposed device due to process variations. The effect of changes in radius, gate oxide thickness, gate length, and channel doping on GAA FET has been discussed in detail.

Investigation of a Gate Stack Gate-All-Around Junctionless Nanowire Field-Effect Transistor for Oxygen Gas Sensing

Investigation of a Gate Stack Gate-All-Around Junctionless Nanowire Field-Effect Transistor for Oxygen Gas Sensing

Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

This research explores a comprehensive examination of gate underlap incorporated strained channel Cylindrical Gate All Around Nanowire FET having enriched performances above the requirement of the 2 nm technology node of IRDS 2025. The device installs a combination of strain engineering based quantum well barrier system in the channel region with high-k spacers sandwiching the device underlaps and stack high-k gate-oxide. The underlaps are prone to parasitic resistance and various short channel effects (SCEs) hence, are sandwiched by HfO2 based high-k. This SCE degradations and a strong electric field in the drain-channel region is rendered controlling the leakages. The strain based Nanosystem engineering is incorporated with Type-II heterostructure band alignment inducing quantum well barrier mechanism in the ultra-thin cylindrical channel region creating an electrostatic charge centroid leading to energy band bending and splitting among the two-fold and four-fold valleys of the strained Silicon layer. This provides stupendous electron mobility instigating high current density and electron velocity in the channel. Thereby, the device is susceptible to on-current enhancement via ballistic transport of carriers and carrier confinement via succumbing of quantum charge carriers. The device transconductance, Ion, Ioff, Ion/Ioff ratio are measured and the output performance (ID-VDS) characteristics is determined providing emphatic enrichments in contrast to the existing gate all-around FETs as well as the 2 nm technology node data of IRDS 2025. Hence, the strained channel Nanowire FET device developed here is presented here as the device of the future for various digital applications, RF applications and faster switching speed.

Investigation of Charge Plasma based Nanowire Field Effect Transistor for Sub 5 nm

In the proposed work, cylindrical Nanowire Field Effect Transistors (NWFETs) are created for sub-10 nm applications using the charge plasma (CP) principle. In the middle of the transistor, a gate is surrounded by an oxide layer and a channel layer. By enclosing the channel in an oxide layer and surrounding it with a distinctive metal layer with various work functions, the charge-plasma concept is introduced. A detailed discussion of device characteristics, such as electric potential and transfer qualities, are presented. For channel lengths of 35 and 10 nm, measurements of the threshold voltage, drain current, and ION/IOFF ratio are analyzed. Sentaurus Technology Computer Aided Design (TCAD) is used to evaluate and analyze the device. TCAD simulations that incorporate the Lombardi mobility model, Shockley-Read-Hall (SRH) model, Density-Gradient model, and Auger recombination models make it easier to calculate tunneling and recombination. Interestingly, the CP-based NWFET produces twice as much output current as its traditional NWFET. Because of the Schottky junction's larger vertical field, significant improvements include the reduction of lateral coupling between the source and drain field lines, the stabilization of the ION/IOFF ratio, an overall reduction in parasitic leakage, and improved scalability. This work extends to circuit implementation, featuring the development of an Inverter circuit. Performance assessments are conducted, and comparisons are drawn with varying channel lengths and widths, further substantiating the efficacy of the proposed structure.

Modeling and Simulation Characteristics of a Highly-Sensitive Stack-Engineered Junctionless Accumulation Nanowire FET for PH3 Gas Detector

In this manuscript, a Stack Engineered Junctionless Accumulation Nanowire FET (SE-JAM-NW FET) has been proposed for low - power and high sensitivity phosphine (PH3) gas detection applications. In comparison to a standard nanowire FET, the SE-JAM-NW FET is used at nanoscale dimensions because of its inherent benefits, including low cost, improved portability, low Off- state current and increased On-state current with low - power consumption. To implement the SE-JAM-NW FET as a phosphine gas sensor, four catalytic metals, Platinum (Pt), Rhodium (Rh), Iridium (Ir) & Palladium (Pd) have been employed as gate electrodes. For designing gas sensor, various electric parameters like potential, electron concentration, recombination rate and electron velocity are evaluated for PH3 gas detection. To forecast the sensor’s response, analog characteristics like changes in drain current, transconductance & output conductance are being simulated for different catalytic metal work functions (200 meV, 150 meV, 100 meV and 50 meV) at the gate electrode. The variation in On-state current-to-Off-state current ratio (IOn/IOff), On-state current (IOn) & subthreshold leakage current (IOff) for sensing the gas molecules has been used to quantify the sensitivity. The effects of silicon pillar-based radius variation and channel length variation on the sensitivity-based parameters are also investigated. Each catalytic metal exhibits improved sensitivity with increased channel length and decreased radius. The outcomes of the ATLAS 3-D device simulator’s numerical simulation closely match with those of the derived analytical model.

Comparing solution-gate and bottom-gate nanowire field-effect transistors on pH sensing with different salt concentrations and surface modifications

Field-effect transistors (FETs) have been developed as pH sensors by using various device structures, fabrication technologies, and sensing film materials. Different transistor structures, like extended-gate (EG) FETs, floating-gate FET sensors, and dual-gate (DG) FETs, can enhance the sensor performance. In this article, we report the effects of using solution-gate and bottom-gate FET configurations on pH sensing and investigate the influence of different ionic concentrations of buffers in the measured signals. The surface charge of hafnium dioxide (HfO2) affected by the buffer pH, with/without the modification of polyethylene glycol (PEG) terminated with hydroxyl groups, and the location of applied gate voltage are vital factors to the sensor performance in pH sensing. Based on the results, the solution-gate FET exhibits good pH sensitivity even in the high ionic strength solutions of bis-tris propane (BTP), and these values of pH sensitivity are close to the Nernst limit (59.2 mV/pH). In general, silane-PEG-OH modification can reduce the deviations of measured signals in pH sensing. The performance of bottom-gate FET is inferior in the BTP buffers with high ionic solutions but suitable to be operated in low ionic concentrations, such as 0.1, 1, and 10 mM BTP buffers. The size of the ions was also studied and discussed. The solution-gate FET demonstrates excellent performance under high ionic strengths, meaning a more significant potential for detecting biological molecules under physiological conditions.

Non‐uniform doping dependent electrical parameters of dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET)

AbstractThis paper presents an analytical analysis of a dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET) possessing a horizontal‐like non‐uniform doping profile. The 2‐D electrostatic potential distribution is evaluated using Poisson's equation under the applicable boundary conditions. Also, the impact of straggle length parameter and the peak doping concentration upon the device behavior is also examined. For authenticating the obtained analytical outcomes, TCAD simulations were also performed. Both the results were contrasted and found to be in good agreement. The outcomes obtained for non‐uniform doped DMGAA‐JAM‐NWFET are also compared with that of uniformly doped DMGAA‐JAM‐NWFET and finer electrical characteristics were noticed for non‐uniformly doped device.

New Approach for Enhancing Sensitivity in Liquid‐Gated Nanowire FET Biosensors Under Optical Excitation

AbstractThe results obtained for liquid‐gated (LG) nanowire (NW) field‐effect transistor (FET) sensors analyzed in divalent ion (MgCl2) solutions, which play a crucial role in the human body, are reported. Liquid‐gated NW FET sensors fabricated in‐house are investigated using I–V characteristics and noise spectroscopy in a wide range of voltages and different intensities of optical infrared irradiation. A new effect is revealed under the influence of external optical excitation. The effect allows for the control of characteristic times of single‐trap phenomena: capture time to a single trap, emission time from the trap, and its ratio represented by the dimensionless ratio parameter (R‐factor). These parameters enabled an improvement in sensor sensitivity. The findings open prospects for controlling charge states in LG NW FET structures to optimize new parameters for achieving ultrahigh sensitivity in biosensors.

Nanowire FETs With Nearly Single-Crystalline Si Channels by NiSi2-Seed Initiated Lateral Epitaxial Crystallization (SILEC)

Nanowire FETs With Nearly Single-Crystalline Si Channels by NiSi₂-Seed Initiated Lateral Epitaxial Crystallization (SILEC)

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, gate oxide material, spacer material, and spacer length. The performance of Improved JL-NWFET is also evaluated in comparison with other structural variants of JL-NWFET. Notably, Improved JL-NWFET showcases an enhancement of 23.1% and 20% in ON-state current (I ON ) and transconductance (g m ), respectively when compared to the conventional JL-NWFET. Furthermore, the Subthreshold Slope (SS) experiences an 88% improvement in the Improved JL-NWFET as opposed to the JL-NWFET. Additionally, the OFF-state leakage current (I OFF ) undergoes a fivefold reduction, leading to a sixfold increase in the I ON /I OFF ratio compared to the JL-NWFET. Among all the variants of JL-NWFET devices analyzed in this paper, Improved JL-NWFET stands out with its exceptional performance characteristics.

Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin

Arrays of silicon nanowire field-effect transistors (Si NWFETs) were built to detect thrombin (a model biomarker) electrically. The Si NWFETs were created using a conventional top-down CMOS process, allowing them to be co-integrated with CMOS readout circuits in the future. EHTES organosilane was then used to graft aptamer probes onto the HfO2 gate oxide of Si nanowires. We investigated the influence of aptamer grafting and thrombin recognition on the electrical transfer capabilities of Si NWFET aptasensors in details. Our technique was evaluated on a significant number of Si NWFETs, including two distinct chips with 30 aptasensors apiece. According to the findings, aptamer grafting increased the threshold voltage by a positive range of +28.8 mV to +87.7 mV, depending on the aptasensor employed. Thrombin identification, on the other hand, resulted in a negative shift of the threshold voltage between −26.6 and − 23.8 mV. These opposing voltage shifts coincide with the aptamer probes' and thrombin molecules' electric charges, respectively. These findings provide unique demonstration of Si NWFETs manufactured utilizing typical top-down CMOS processing methods, allowing these devices to be used in various biomedical and biosensing applications.

(Invited) BEOL-Compatible Oxide Semiconductor Logic and Memory Devices

3D monolithic integration of logic and memory devices has emerged as one of the key enablers for next-generation electronic devices to address the ever-increasing demand for higher integration density, better performance and energy efficiency. BEOL-compatible oxide semiconductors show great potential to revolutionize the field thanks to their unique properties [1].We present our recent advancement related to BEOL-compatible oxide semiconductors for logic and memory applications. The digital-etch-enabled nanowire transistors and α-IGZO-based eDRAM will first be discussed, followed by the ferroelectric (FE) memories with high performance and novel structures utilizing α-IGZO or ALD-deposited ZnO as the channel.Ultra-scaled amorphous IGZO (α-IGZO) nanowire field-effect transistors (NW-FETs) hold great potential for applications demanding high performance and integration density. To realize the fabrication of high-quality and aggressively-scaled nanowire structures, a novel digital etching method for amorphous α-IGZO materials has been proposed and demonstrated [2]. Confirmed by the SEM images of an α-IGZO nanowire before and after digital etching, a notable nanowire width W NW reduction can be observed. We have the thinnest α-IGZO nanowire achieved by the digital etching with a W NW of approximately 20 nm. By further developing the transistor upon the nanowire, the α-IGZO NW-FET attains a good subthreshold swing (SS) of 80 mV/decade and a high peak extrinsic transconductance (G m, ext) of 612 μS/μm at V DS of 2 V (456 μS/μm at V DS = 1 V). Compared to the previous studies, our IGZO NW-FET achieves one of the highest peak G m values among all IGZO-based FETs.Besides the BEOL compatibility and high on-current, ultra-low subthreshold leakage makes α-IGZO FETs extremely promising for eDRAM. We further investigated the potential of α-IGZO eDRAM by developing the charge-domain compute-in-memory (CiM) [3]. Experiments have demonstrated small SS, large on-state current, and long-time charge retention with our dedicated 4T1C memory cell. With differential cell structure, an even higher tolerance for charge loss can be attained. With experiment-calibrated benchmarking in the VGG-8 network for CIFAR-10 image classification tasks, 2092 TOPS/W power efficiency for the CiM core can be expected, outperforming the prior TFT and CMOS-based CiM approaches, exhibiting significant advantages for ultra-low-power applications.The integration of doped-HfO2 FE material and oxide semiconductor, both BEOL-compatible with large-scale and cost-effective deposition, presents a promising avenue for advancing data storage in the future. We have developed the high-performance α-IGZO Fe-FET with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure as well as the Fe TCAM [4]. The α-IGZO Fe-FET achieves a large memory window of ~3 V with high reliability, while the Fe TCAM reduces the transistor number from 16 to 2 compared to the traditional SRAM-based one. Besides α-IGZO, we believe that ALD-based oxide semiconductors featuring high controllability of film thickness and conformal coverage of the 3D structures can create new opportunities for novel device structure and integration. The fin-gate ZnO Fe-FET stands for a great example while not only outstanding device performance but also suppressed device-to-device variation due to the unique structure have been demonstrated, holding tremendous promise for high-density 3D integration [5]. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114).

(Invited) In-Depth Understanding of the Key Contributors to the Total Flicker Noise in Advanced Logic Devices

The aim of this work is to perform an in-depth analysis in order to identify the key contributors to the total flicker noise in advanced MOSFET technologies, e.g. UTBOX, FinFET or Gate-all-around (GAA) nanowire or nanosheet FET devices.In this abstract, as an example, we will focus on p-type gate all around silicon vertical nanowire devices fabricated at imec. The transistors have a fixed gate length (LG) of 50 nm and 1200 nanowires in parallel (N), each nanowire (NW) having a diameter (WNW) of 20 nm. The total width (W) of the device is calculated as . The gate stack corresponds to an equivalent oxide thickness (EOT) of 0.9 nm. A full description of the process flow of the devices is presented in [1]. Comparison between the Y-function strategy of [2] and McLarty methodology [3] permits to estimate with accuracy the DC parameters necessary for low frequency noise modelling, which are summarized in Table 1.Typical low frequency noise spectra are shown in Figure 1. The methodology for the estimation of the low frequency noise parameters is described in [4], but it is obvious that the noise spectra are dominated by 1/f noise and only few Lorentzian contributions appear for some gate voltage polarization. As the corresponding flicker noise levels (K f ), plotted in Figure 2 present a plateau and rise with the increase of the applied gate voltage, the responsible 1/f noise mechanism should be related to the carrier number or correlated carrier number fluctuations mechanism, with a possible contribution of the access resistance 1/f noise.Firstly, the model described in [5-9] expressed as in equation (1) is employed. A linear dependence of the square root of the 1/f noise levels on the measured Id/gm is observed in Figure 3, permitting to estimate from the intercept and slope the flat-band noise level (Svfb) and the W coefficient, respectively. Using the methodology of [9] the estimated W parameter is corrected by the access resistance influence. Good agreement with experimental data in strong inversion may be observed in both cases (Figure 4).Secondly, the model which considers the small signal model of the MOSFET is used, assuming that the channel resistance noise and access resistances noise are uncorrelated noise sources [2,10,11]. The model may be expressed by equation (2) ((13) of [11]), in order to make no assumption concerning the gm/gch ratio. Beyond the threshold voltage, the impact of the cannot be neglected, as observed from Figure 5. It may be observed from Figure 6 that the correlated number fluctuation and mobility noise mechanism cannot explain the flicker noise behavior in very strong inversion, and an additional contribution of the access resistances noise may be considered in order to agree with the experimental data.The noise parameters estimated to agree with the experimental data for both models are summarized in Table 2. It is interesting to note that the experimental data may be explained by both models, but the key contributors are not the same: only correlated number fluctuations and mobility noise mechanism for the first model, and correlated number fluctuations and mobility and access resistance noise mechanisms contribution for the second one. Moreover, the estimated flat-band noise levels are not the same, a much lower Svfb is obtained when the first model is employed. Considering the access resistance impact may correct the W coefficient, but leads to even lower flat-band noise levels, as already reported in [9].These results lead to some questioning about which of these two models is most accurate and give good indications on the key contributors and estimated parameters of the total flicker noise.