Investigation of Charge Plasma based Nanowire Field Effect Transistor for Sub 5 nm

Abstract

In the proposed work, cylindrical Nanowire Field Effect Transistors (NWFETs) are created for sub-10 nm applications using the charge plasma (CP) principle. In the middle of the transistor, a gate is surrounded by an oxide layer and a channel layer. By enclosing the channel in an oxide layer and surrounding it with a distinctive metal layer with various work functions, the charge-plasma concept is introduced. A detailed discussion of device characteristics, such as electric potential and transfer qualities, are presented. For channel lengths of 35 and 10 nm, measurements of the threshold voltage, drain current, and ION/IOFF ratio are analyzed. Sentaurus Technology Computer Aided Design (TCAD) is used to evaluate and analyze the device. TCAD simulations that incorporate the Lombardi mobility model, Shockley-Read-Hall (SRH) model, Density-Gradient model, and Auger recombination models make it easier to calculate tunneling and recombination. Interestingly, the CP-based NWFET produces twice as much output current as its traditional NWFET. Because of the Schottky junction's larger vertical field, significant improvements include the reduction of lateral coupling between the source and drain field lines, the stabilization of the ION/IOFF ratio, an overall reduction in parasitic leakage, and improved scalability. This work extends to circuit implementation, featuring the development of an Inverter circuit. Performance assessments are conducted, and comparisons are drawn with varying channel lengths and widths, further substantiating the efficacy of the proposed structure.