Nanosheet Channel Research Articles

Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

We analyzed the performance, power, area of 3 nm node fin and nanosheet (NS) field-effect transistors (FETs) implementing buried power rail (BPR) after full calibration to 5 nm node hardware. Fin-shaped FETs (FinFETs) have smaller <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> delay than do NS FETs (NSFETs) under the same footprint and two-fin configuration. Larger number of NS channels boost drive currents but also increase gate capacitances as a tradeoff. Compared with 7 and 3 nm standard cells achieve 75% cell area scaling in average. Cells using BPR decrease delay, transition time, internal power, and pin capacitances under the same area. Larger cells such as D-flip flop (DFF) and XOR decrease those further because the parasitic capacitances of metal layers between signal and power/ground decrease much. NS-based cells using BPR can improve delay and transition time by increasing the number of NS channels, but increase internal power and pin capacitance. Overall, fin-based cells using BPR have smaller energy delay product by 12% compared with those without BPR and by 10% compared with NS-based cells using BPR.

Performance Evaluation of Scaled ZnO Stacked Nanosheet Channel Ternary Field Effect Transistor

Ternary logic device technologies have been actively researched due to the potential benefits such as lower power consumption, smaller device count, smaller area, and higher data processing density, compared to their binary counterparts. In this work, scaling prospect of ZnO stacked nanosheet channel ternary field effect transistor has been investigated. The benefits of scaling geometric parameters such as gate dielectric thickness, channel length, and source/drain charge injection area are examined. 90 % lower power consumption in the intermediate state is achieved at Vdd = 1 V with a noise margin of 130 mV, compared to other emerging ternary logic devices. The feasibility for stable ternary circuit operation is confirmed as well.

Inkjet‐Printed MoS2 Transistors with Predominantly Intraflake Transport

Abstract2D semiconductors, such as transition metal dichalcogenides (TMDs) show a rare combination of physical properties that include a large‐enough bandgap to ensure sufficient current modulation in transistors, matching electron and hole mobility for complimentary logic operation, and sufficient mechanical flexibility of the nanosheets. Moreover, the solvent‐exfoliated TMD‐nanosheets may also be processed at low temperatures and onto a wide variety of substrates. However, the poor inter‐flake transport in solution‐cast 2D‐TMD network transistors hinders the realization of high device mobility and current modulations that the intraflake transistors can regularly demonstrate. In this regard, fully printed and electrolyte‐gated, narrow‐channel MoS2 field‐effect transistors (FETs) with simultaneous high current saturation (&gt;310 µA µm−1) and on–off ratio (&gt;106) are proposed here. The transport limitation is overcome by printing an additional metal layer onto the 2D‐TMD nanosheet channel, which substantially shortens the effective channel lengths and results in predominant intraflake transport. In addition, a channel‐capacitance‐modulation induced subthermionic transport is recorded, which leads to a subthreshold slope value as low as 7.5 mV dec−1. On the other hand, thermionic MOSFETs and fully printed depletion‐mode NMOS inverters are also presented. The demonstrated generic approach involving chemically exfoliated nanosheet inks and the absolute device yield indicates the feasibility of fully printed 2D‐TMD electronics.

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

This work reports on low temperature epitaxial growth solutions for the processing of advanced CMOS devices beyond the 3 nm technological node. The complex stacking of highly compositionally contrasted strained group IV materials is first demonstrated at 500°C. It enables the formation of active nanosheet channels with bottom isolation, necessary for ultimate transistor scaling. Using high order Si and Ge precursors also offers great opportunities for the epitaxy of advanced source/drain materials. It allows achieving hole active concentrations as high as 1.3x1021 cm-3 in in-situ B-doped Si0.5Ge0.5, providing Ti / SiGe:B contacts with low specific resistivity. Grown at temperatures as low as 400°C, the epilayers deposit in a conformal manner, thereby wrapping high aspect ratio 3-dimensional structures and maximizing the contact areas, being an additional option to further decrease device access resistances. As an alternative to B-doping only, we also demonstrate uniformly Ga-doped materials with concentrations ~ 1x1020 cm-3. B and Ga are finally combined to co-dope SiGe and further reduce the Ti / p-SiGe contact resistivity.

Electro-Thermal Performance Boosting in Stacked Si Gate-all-Around Nanosheet FET With Engineered Source/Drain Contacts

In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through S/D trenched regions in addition to the conventional scheme where metal (M0) epi on the S/D. The device ET performance is enhanced by increasing the device on-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) by more than 10% with better device lattice heat removal from the hot-spot location of the NSHFET. This results in decreased device self-heating by lowering lattice hot-spot temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L, max</sub> ) and device effective thermal resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th, eff</sub> ) by more than 11% compared to conventional M0-epi-based NSHFET design. The junction temperature difference between the nanosheet channels is also lowered, which decreases the inter-sheet threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) difference. The benchmarking study of the device designs reveals that M0-trench-based NSHFET gives the best performance from both electrical and thermal perspective for future sub-5-nm CMOS logic technologies.

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

On-Current Enhancement in TreeFET by Combining Vertically Stacked Nanosheets and Interbridges

The TreeFET channel, which is a combination of vertically stacked nanosheet channels and fin-shaped interbridge channels in between the nanosheets, can provide an additional channel conduction area to improve the on-current without increasing the device footprint. To provide on-current enhancement, a minimum height is required for the interbridge that is dependent on the width of the interbridge and the physical gate oxide thickness. Minimizing the threshold voltage difference between the interbridges and the nanosheet channels also plays a crucial role in the optimization of the on-current of TreeFETs. The design criteria for TreeFETs are studied using TCAD simulation of Ge nFETs.

Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors

Using physics-based predictive technology CAD simulations, we show the improvements possible in device performance via strain engineering in vertically-stacked horizontal gate-all-around nanosheet Field-Effect transistors (NSFETs), which may outperform conventional FinFETs beyond 7 nm technology node. Effects of mechanical strain on NSFET variability is reported for the first time. We present a novel simulation approach for the analyses of random dopant fluctuation (RDF) and metal grain granularity (MGG) dependent variability in nanosheet transistors. The study encompasses topography simulation, which realistically reproduces a reported experimental nanosheet transistor. Device simulations are based on sub-band Boltzmann transport with 2D Schrödinger equation in the nanosheet cross-section and 1D Boltzmann transport along the nanosheet channel. The effects of mechanical stress and geometry dependence of the electrical characteristics are also reported. Critical design issues are outlined.

Performance of Junctionless and Inversion-Mode Thin-Film Transistors With Stacked Nanosheet Channels

This article comprehensively investigated a junctionless thin-film transistor (JL TFT) with stacked nanosheet (NS) channels. Through experiments, we 1) compared a JL TFT with a single NS channel and a JL TFT with stacked NS channels and 2) compared an inversion-mode TFT with stacked NS channels and the JL TFT with stacked NS channels; the TFTs were fabricated using Si-based technology. The JL TFT with stacked NS channels exhibited a subthreshold slope of 135 mV/dec and drain-induced barrier-lowering value of 50.8 mVV−1, which were superior to those of the other devices. Furthermore, we simulated another device with a hybrid P/N/P channel structure based on the JL TFT by using three-dimensional technology computer aided design (3D TCAD) simulation. According to the study results, the JL TFT with stacked NS channels is a promising candidate for scaling down Si TFTs and for use in advanced 3D applications.

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs

The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The Vt difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher Vt difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The Vt difference increases with the increasing channel number and nanosheet width.

Study of line edge roughness on various types of gate-all-around field effect transistor

The impact of line edge roughness (LER) on gate-all-around FETs (GAAFETs) with various channel types is investigated. Among various channel types of GAAFET, (i) nanowire (NW), (ii) nanosheet (NS), and (iii) stacked channel are investigated. Considering the Si/SiGe stacking and selective etching process (which is commonly used to release the channel of GAAFET), we modeled the LER profile for channels. Moreover, 3D LER modeling is adopted to represent the LER profile in non-planar device structure. It turned out that the NS channel GAAFET has not only higher on-state drive current but also better performance variation immunity than the NW channel GAAFET. This is because the aspect ratio of channel affects the LER profile. Compared against single-channel GAAFET, the stacked channel GAAFET has better variation immunity because of its complementary effect in-between stacked channels. To investigate the impact of complementary effect, we simulated two different stacked channels, one of which has no correlation between stacked channels, and the other of which has the correlation induced from the channel-releasing processing step. It turned out that the stacked channel GAAFET with no correlation in-between the channels can have better variation-robustness.

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

By using technology computer aided design (TCAD) simulation, the aim of this paper is to investigate the effect of Si parasitic channel, which is placed under stacked nanosheet channels, on electrical characteristic of stacked nanosheet GAA FETs. We have controlled the parasitic channel height, and evaluated the effect on electrical performance of the device. Trade-off in performance of the nanosheet FET is observed: the increase in parasitic channel height results in improvement in subthreshold swing and on/off ratio, while the increase in capacitance brings worse RC delay and active power. The parasitic channel height control in devices with ground plane doping is also investigated.

Constructing hierarchical lanthanum-doped nickel hydroxidenitrate nanoflowers with dilated lattice spacing for improving asymmetric supercapacitors

The novel lanthanum-doped nickel hydroxidenitrate (LaNiHN) nanoflowers are prepared by a facile one-step solvothermal growth method. The doping of La ions into the lattice of the NiHN nanoflowers can effectively increase the electrical conductivity, lattice volume and c-axis spacing of NiHN nanosheets and lead to rapid transfer of electrolyte ions and electrons between the nanosheet channels, resulting in a high specific capacity of 154 mAh g−1 (at 1 A g−1) and high rate performance for supercapacitor positive electrode. Moreover, the Fe2O3 supported on graphene nanosheets (Fe2O3/GNS) with high specific capacity and excellent stability is selected as negative electrode to match the LaNiHN nanoflowers positive electrode for assembly of a novel LaNiHN//Fe2O3/GNS asymmetric supercapacitor (ASC). By virtue of their excellent electrochemical properties and complementary working voltage, the as-assembled ASC possesses a wide operating voltage of 1.65 V, high energy density of 51 Wh kg−1 at a power density of 825 W kg−1, as well as the acceptable cycling stability of 87% capacity retention after 5000 cycles.

Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure

This paper demonstrates the gate-all-around P/N hybrid nanosheet p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high on/off current ratio (>5 × 106), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel and three-dimensional stacked ICs applications.

(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors

Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels, a specific SiGe/Si superlattice epitaxy is employed, with SiGe being used as a sacrificial layer that will define the suspension thickness (Tsus) between the channels. In this paper, we will consider the optimization of SiGe/Si multilayer epitaxy for Nanosheet channel definition (Fig. 1). Stacks with different Ge compositions are physically characterized and studied. With strain characterization and x-ray diffraction measurements on (100) substrates, we will show that it is possible to form pseudomorphic defect-free SiGe/Si multilayers over a wide range of Ge concentrations in the sacrificial SiGe (Fig. 2 and 3). The uniformity obtained on blanket 300mm substrates will be presented (Fig. 4), with a discussion on the SiGe/Si interface abruptness. In the context of CMOS device integration, it is necessary to employ a low temperature STI process to mitigate the Ge inter-diffusion in the silicon channel and to avoid the possible generation of defects from plastic relaxation of SiGe. The SiGe and Ge-Si intermixed regions are removed with appropriate selective etch process in two Nanosheet specific modules: inner spacer formation in the extension regions (Fig. 5) and post channel release in the gate regions (Fig. 6), leaving only 5nm intrinsic silicon Nanosheets. We will report the etch rate and selectivity of our in-house vapor-phase channel release process performed at low temperature. This process enables us to remove SiGe versus Si with a great selectivity and a limited amount of silicon loss during channel release, before gate stack deposition around the stacked Nanosheets. From a device perspective, we will show that the optimization of the silicon thickness in the SiGe/Si superlattice plays an important role in the Nanosheet device performance and electrostatics (Fig. 7). Finally, with a good SiGe/Si multilayer uniformity control, a reduced thermal budget and after optimization of our in-house SiGe selective etch process, we will show the capability to form 5nm silicon Nanosheet channels with small within wafer variation, low device variability and good process control, compatible with the fabrication of very large scale integrated circuits for future CMOS device nodes. Acknowledgements: This work was performed by the Research Alliance Teams at various IBM Research Facilities. Figure 1

Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.

Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of &amp;gt;108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL &amp;lt; 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to &amp;lt;1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.

Electrochemical synthesis of a ternary transition metal sulfide nanosheets on nickel foam and energy storage application

We report growth of nickel cobalt sulfide (NCS) ultrathin nanosheets directly on Ni foam substrate by a facile and novel electrodeposition method. The as-prepared NCS sample is used as an electrode material for supercapacitor application due to their large electrochemically active surface area and interconnected nanosheet channels for the facilitation of ion transportation. The NCS nanosheets possess enhanced electrochemical performance in terms of fast and high reversible faradaic reactions characterized by prominent oxidation and reduction peaks. NCS nanosheets showed an ultrahigh specific capacitance of 1712 Fg−1 at a current density of 1 Ag−1 with excellent cyclic stability. The excellent supercapacitor performance of NCS nanosheets can be attributed to its rich redox reactions as well as high transport rate for both electrolyte ions and electrons.

Temperature dependence of charge transport in zinc oxide nanosheet source-gated transistors

In the present work, we report the high performance of zinc oxide (ZnO) nanosheet (NS) based source-gated transistors (SGTs) with asymmetric Schottky source and ohmic drain contacts: low saturation drain-source voltages (~2V) in the output scans (even at high gate voltages), high current on/off ratio (>107) and low off-currents (0.1pA). For a deeper understanding of the device mechanism and charge transport at metal–semiconductor contact interface, temperature dependent current–voltage studies have been performed. They revealed that the device operation can be ascribed to 3 main processes: i) the reverse biased Schottky source contact, which essentially controls charge carrier injection in to the NS channel, ii) effective manipulation of the source barrier by the gate field and iii) modulation of the depletion region beneath the source contact. These results are likely to improve the future generations of the ZnO based SGTs which offer several advantages for thin-film transistor design, including low power dissipation, small signal amplification, and as active load for the electronic circuits.