(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

Abstract

This work reports on low temperature epitaxial growth solutions for the processing of advanced CMOS devices beyond the 3 nm technological node. The complex stacking of highly compositionally contrasted strained group IV materials is first demonstrated at 500°C. It enables the formation of active nanosheet channels with bottom isolation, necessary for ultimate transistor scaling. Using high order Si and Ge precursors also offers great opportunities for the epitaxy of advanced source/drain materials. It allows achieving hole active concentrations as high as 1.3x1021 cm-3 in in-situ B-doped Si0.5Ge0.5, providing Ti / SiGe:B contacts with low specific resistivity. Grown at temperatures as low as 400°C, the epilayers deposit in a conformal manner, thereby wrapping high aspect ratio 3-dimensional structures and maximizing the contact areas, being an additional option to further decrease device access resistances. As an alternative to B-doping only, we also demonstrate uniformly Ga-doped materials with concentrations ~ 1x1020 cm-3. B and Ga are finally combined to co-dope SiGe and further reduce the Ti / p-SiGe contact resistivity.