(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

Abstract

The epitaxial growth of group IV semiconductor materials is one of the backbones of modern IC production flows. At present nodes it is used for the Source/Drain (S/D) engineering of both p- and n-MOS high performance transistors, allowing the deposition of SiGe:B and Si:P layers with active carrier concentrations ~ 1x1021 cm-3, ensuring low contact resistivities [1]. However, with reducing device dimensions, the growing importance of contact resistance in devices remains a major concern. A significantly lower parasitic S/D resistance could also be obtained thanks to the use of epitaxial and metal wrapped-around contacts (WAC) [2]. In addition, alternatives to Si channel materials (SiGe or Ge) and new device concepts such as 3D transistor stacking, complementary FET (CFET) and gate-all-around (GAA) nanosheet devices, all considered for the upcoming technological nodes of 3 nm and below [3], require process temperatures < 500ºC.To meet these temperature requirements, epitaxial processes based on the combination of high order Si and Ge precursors are explored together with low temperature Cl2 etching. The strength of this approach has already been demonstrated by the successful implementation of Ge/SiGe stacks and Ge S/D deposited at low temperature for the production of pMOS Ge GAA devices exhibiting excellent electrostatic control at sub-30 nm gate lengths [3].In this contribution, we use advanced low temperature epitaxial processes to enable cutting-edge applications. Complex and highly strained multi stacks are pseudomorphically grown with a limited thermal budget. The compositional contrast between the different parts of the stack, combined with very sharp interfaces, allows for the selective removal of sacrificial layers and the formation of active channels being totally isolated from parasitic channels in the substrate (Fig. 1(a)). In addition, highly B (Fig. 1 (b)) or B+Ga co-doped SiGe layers are grown at temperatures down to 400ºC with an active doping concentration exceeding 1x1021 cm-3. Epitaxial WAC structures are finally demonstrated Fig. 1 (c).[1] H. Wu et al., IEDM, 819 (2018)[2] S. Chew et al., 2017 IEEE Int. Interconnect Techn. Conf. (IITC), 1 (2017)[3] E. Capogreco, et al., Symposium on VLSI Technology , T94 (2019) Fig. 1. Example applications for advanced low temperature epitaxial growth processes. (a) HAADF-STEM cross-section image of a SiGe/Si multi stack used for the fabrication of nanosheet device with integrated bottom SiN/SiCO isolation; (b) B concentration profile measured by SIMS on a SiGe:B layer grown at low temperature, resulting in a carrier concentration above ~1x1021 cm-3. (c) Low temperature SiGe:B grown on Si fins demonstrating epitaxial WAC. Figure 1