Nanoscale Memory Devices Research Articles

Solution-Processed NiPS3 Thin Films from Liquid Exfoliated Inks with Long-Lived Spin-Entangled Excitons.

Antiferromagnets are promising materials for future opto-spintronic applications since they show spin dynamics in the THz range and no net magnetization. Recently, layered van der Waals (vdW) antiferromagnets have been reported, which combine low-dimensional excitonic properties with complex spin-structure. While various methods for the fabrication of vdW 2D crystals exist, formation of large area and continuous thin films is challenging because of either limited scalability, synthetic complexity, or low opto-spintronic quality of the final material. Here, we fabricate centimeter-scale thin films of the van der Waals 2D antiferromagnetic material NiPS3, which we prepare using a crystal ink made from liquid phase exfoliation (LPE). We perform statistical atomic force microscopy (AFM) and scanning electron microscopy (SEM) to characterize and control the lateral size and number of layers through this ink-based fabrication. Using ultrafast optical spectroscopy at cryogenic temperatures, we resolve the dynamics of photoexcited excitons. We find antiferromagnetic spin arrangement and spin-entangled Zhang-Rice multiplet excitons with lifetimes in the nanosecond range, as well as ultranarrow emission line widths, despite the disordered nature of our films. Thus, our findings demonstrate scalable thin-film fabrication of high-quality NiPS3, which is crucial for translating this 2D antiferromagnetic material into spintronic and nanoscale memory devices and further exploring its complex spin-light coupled states.

On the structural and magnetic properties of Sr-substituted LaMnO3 nanoparticles (La1-xSrxMnO3)

In this study, nanocrystalline lanthanum strontium manganite, La1-xSrxMnO3 (x = 0.2, 0.3, 0.4, 0.5, 0.6) where Sr substitutes in La-site are synthesized by sol–gel auto-combustion technique and annealed at 800 °C for 2hr. X-ray diffraction (XRD) study reveals the formation of a single phase rhombohedral crystal structure in all the samples. The crystallite size is calculated from Scherrer formula and the Williamson-Hall plot wherein the crystallite size are found to decrease with Sr substitution. Uniform and dense morphological structure are observed in the FESEM micrographs with average particle size ranging from 30 nm to 60 nm. Magnetic properties studied by using vibrating sample magnetometer (VSM) show decrease in saturation magnetization with increase in Sr substitution which demonstrates that ferromagnetic order is weakened and magnetic disorder increases. The maximum saturation magnetization of 32.8 emu/g is observed in La0.7Sr0.3MnO3 and has the most appropriate ratio of Mn4+: Mn3+ ≈ 1 for maximum double exchange interaction. The particle size of the nanoparticles is also found to affect the magnetocrystalline anisotropy of the system and observed to be in the order of 105 erg/cm3. These ferromagnetic LSMO along with their semi-metallic behaviour may be potentially utilised in nanoscale non-volatile memory and future spintronic devices.

NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing

Emerging two-terminal nanoscale memory devices, known as memristors, have demonstrated great potential for implementing energy-efficient neuro-inspired computing architectures over the past decade. As a result, a wide range of technologies have been developed that, in turn, are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors’ attributes in novel neuro-inspired topologies. In this study, we present NeuroPack, a modular, algorithm-level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to choose from a variety of neuron models, learning rules, and memristor models. Its hierarchical structure empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameter options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.

Van der Waals Antiferroelectric Magnetic Tunnel Junction: A First-Principles Study of a CrSe2/CuInP2S6/CrSe2 Junction.

Magnetic tunnel junctions (MTJs), ferroelectric/antiferroelectric tunnel junctions (FTJs/AFTJs), and multiferroic tunnel junctions (MFTJs) have recently attracted significant interest for technological applications of nanoscale memory devices. Until now, most of them are based on perovskite oxide heterostructures with a relatively high resistance-area (RA) product and low resistance difference unfavorable for practical applications. The recent discovery of the two-dimensional (2D) van der Waals (vdW) ferroelectric (FE) and magnetic materials has opened a new route to realize tunnel junctions with high performance and atomic-scale dimensions. Here, using first-principles calculations, we propose a new type of 2D tunnel junction: an antiferroelectric magnetic tunnel junction (AFMTJ), which inherits the features of both MTJ and AFTJ. This AFMTJ is composed of monolayer CuInP2S6 (CIPS) sandwiched between 2D magnetic electrodes of CrSe2. The AFTJ with nonmagnetic electrodes of TiSe2 on both sides of CIPS and the asymmetric AFTJ with both CrSe2 and TiSe2 electrodes are also investigated. Based on quantum-mechanical modeling of the electronic transport, sizeable tunneling electroresistance effects and multiple nonvolatile resistance states are demonstrated. More importantly, a remarkably low RA product (less than 0.1 Ω·μm2) makes the proposed vdW AFMTJs superior to the conventional MFTJs in terms of their promising nonvolatile memory applications. Our calculations provide new guidance for the experiment and application of nanoscale memory devices.

Smart Design of Resistive Switching Memory by an In Situ Current‐Induced Oxidization Process on a Single Crystalline Metallic Nanowire

AbstractResistive switching random access memory (ReRAM) has recently generated significant interest due to its potentials used in nanoscale logic, memory devices, and neuromorphic applications. From the device physics, a uniform dielectric layer is necessary to access as the main switching layer to perform stable resistive switching. This, however, makes the fabrication process more challenging. In this regard, a design of resistive switching memory by an in situ current‐induced oxidization process on a single crystal metallic nanowire (NW) is demonstrated where a single crystal Cu NW is found as the best material with stable switching behaviors after the in situ current‐induced oxidization process. With the in situ current‐induced oxidization process by high current density on the Cu NW, a reversible resistive switching up to 100 cycles with a large ON/OFF ratio of >103 and a low switching voltage of <0.5 V can be obtained. The initial current‐induced oxidation provides a core–shell (Cu2O/Cu) nanowire structure that contributed to the switching properties. The possible switching mechanisms and potential guidelines are systematically proposed. The current work opens up the opportunities to design the ReRAM device with full‐ metallic materials.

Two-Dimensional Antiferroelectric Tunnel Junction.

Ferroelectric tunnel junctions (FTJs), which consist of two metal electrodes separated by a thin ferroelectric barrier, have recently aroused significant interest for technological applications as nanoscale resistive switching devices. So far, most existing FTJs have been based on perovskite-oxide barrier layers. The recent discovery of the two-dimensional (2D) van der Waals ferroelectric materials opens a new route to realize tunnel junctions with new functionalities and nm-scale dimensions. Because of the weak coupling between the atomic layers in these materials, the relative dipole alignment between them can be controlled by applied voltage. This allows transitions between ferroelectric and antiferroelectric orderings, resulting in significant changes of the electronic structure. Here, we propose to realize 2D antiferroelectric tunnel junctions (AFTJs), which exploit this new functionality, based on bilayer In_{2}X_{3} (X=S, Se, Te) barriers and different 2D electrodes. Using first-principles density functional theory calculations, we demonstrate that the In_{2}X_{3} bilayers exhibit stable ferroelectric and antiferroelectric states separated by sizable energy barriers, thus supporting a nonvolatile switching between these states. Using quantum-mechanical modeling of the electronic transport, we explore in-plane and out-of-plane tunneling across the In_{2}S_{3} van der Waals bilayers, and predict giant tunneling electroresistance effects and multiple nonvolatile resistance states driven by ferroelectric-antiferroelectric order transitions. Our proposal opens a new route to realize nanoscale memory devices with ultrahigh storage density using 2D AFTJs.

MemCAM: A Hybrid Memristor-CMOS CAM Cell for On-Chip Caches

Non-volatile nanoscale memory devices (such as memristors) have promised to overcome the challenges of scalability and leakage currents of CMOS based memory devices. These novel memories can be fabricated in back-end-of-the-line of any CMOS process. Currently, a lot of research is focused on investigating the benefits of memristors for associative memories. These are Content-Addressable Memories (CAM) in which search based data access takes place. Searching for a particular bit in memristor is time consuming while search in CMOS CAM zone is efficient. To combine the speed and ease of search of CMOS memory and the scalability of memristor memory, we present a novel multibit hybrid CMOS-Memristor Associative Memory Cell. The benefits of such memory cells manifest in on-chip caches - the instruction and data cache, Branch Target Buffer, and Translation Lookaside Buffer. To exemplify the benefit of the cell further, we also simulate the MemCAM as the TLB of an ARM processor and obtained upto 50% decrease in miss rates of Data TLB and upto 93% in that of Instruction TLB. Average speedup of 1.16 was also achieved on various benchmark applications of PARCSEC and MiBench suites.

Impact of process-induced variability on the performance and scaling of Ge2Sb2Te5 Phase-change memory device

The process-induced variability in nanoscale phase-change memory (PCM) devices is of utmost importance for the development of reliable single-bit/multi-bit data storage devices. In this study, the influence of structural and interfacial parameters on the performance of Ge2Sb2Te5 (GST) PCM device is systematically investigated using Plackett–Burman design of experiment method. Five important structural parameters, (i) heater (TiN) radius (HR), (ii) heater height, (iii) GST radius (WGST), (iv) GST thickness, and (v) top electrode thickness, and along with three interfacial parameters namely, (i) thermal boundary resistance (TBR) between GST and TiN interface (ii) TBR between GST and SiO2 interface, and (iii) electrical interface resistance (EIR) between GST and TiN interface are considered for the study. Furthermore, to understand the impact of scaling, the performance metrics i.e. RESET resistance (RRESET), SET resistance (RSET), RESET power (PRESET) and SET power (PSET) of an isotropically scaled-down device with a HR of 10 nm are extracted and compared against the reference device of 50 nm HR. The TCAD simulation results reveal that HR and WGST are the most dominant structural parameters for the output metrics and the analysis shows that ratio should be maintained between 2.7 and 4.5 to offer reliable RESET operation. Among the interfacial parameters, GST/TiN EIR is the most significant controlling parameter for PRESET/PSET metrics, whereas GST/TiN TBR plays an important role in achieving better RRESET/RSET. Hence, our findings of the most and least sensitive input parameters can be effectively used for the better optimization of RESET/SET pulse parameters to achieve reliable programming of PCM devices in the future technology nodes.

Quantum scattering and its impact on the source–drain current with defect generation in the channel of nanoscale transistors

The electrons scattered by the defects in the channel can be described by the time-dependent Schrodinger equation. An analytical and physical model of the time evolution of the source–drain current in a transistor at a given defect density has been proposed. It clearly shows that the source–drain current is composed of direct-current and a lot of alternating-current components. And thus the source–drain current will be sensitive to the defect density in the channel. Further, an analytical and physical relation between the phase shift of alternating-current components and the defect density in the channel is derived. Phase shift obtained from time-evolution experimental data of the source–drain current in aging process of nanoscale memory devices agrees well with the theoretical prediction.

Switchable Polarization in Mn Embedded Graphene

Graphene, despite its many unique properties, is neither intrinsically polar due to inversion symmetry nor magnetic. However, based on density functional theory, we find that Mn, one of transition metals, embedded in single or double vacancy (Mn@SV and Mn@DV) in a graphene monolayer induces a dipole moment perpendicular to the sheet, which can be switched from up to down by Mn penetration through the graphene. Such switching could be realized by an external stimuli introduced through the tip of a scanning probe microscope, as already utilized in the studies of molecular switches. We estimate the energy barriers for dipole switching, which are found to be 2.60 eV and 0.28 eV for Mn@SV and Mn@DV, respectively. However, by applying biaxial tensile strain, we propose a mechanism for tuning the barrier. We find that 10% biaxial tensile strain, which is already experimentally achievable in graphene-like two-dimensional materials, can significantly reduce the barrier to 0.16 eV in Mn@SV. Moreover, in agreement with previous studies, we find a high magnetic moment of 3 μB for both Mn@SV and Mn@DV, promising the potential of these structures in spintronics as well as in nanoscale electro-mechanical or memory devices.

Defect-mediated vortex multiplication and annihilation in ferroelectrics and the feasibility of vortex switching by stress

The possibility of switching the direction of the dipole toroidal moment in ferroelectrics provides exciting opportunities for development of novel nanoscale memory and logic devices. However, a practical control of vortex chirality is rather challenging at present stage, not to mention via mechanical methods. In this paper, we performed the phase-field simulations to show that mechanical switching of vortex chirality can be achieved in ferroelectric nanoplatelet via defect engineering. After introducing a void defect in the nanoplatelet, relative stability of single-vortex state and multi-vortices state is found to be altered. Importantly, during stress-induced vortex multiplication process, the void is a favored nucleation core of new vortex; meanwhile, vortices tend to annihilate away from the void during a vortex annihilation process. As the favored regions of vortex nucleation and annihilation are not the same, a deterministic mechanical switching of vortex chirality can be achieved. The effects of temperature, shape of the nanoplatelet, void size, as well as void position, on the defect-mediated vortex switching behaviors are systematically revealed. Our study demonstrates the feasibility of vortex switching by mechanical loads and provides a route to control and develop electromechanical devices based on ferroic vortices.

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices.

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag5In5Sb60Te30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

Temporal correlation detection using computational phase-change memory

Conventional computers based on the von Neumann architecture perform computation by repeatedly transferring data between their physically separated processing and memory units. As computation becomes increasingly data centric and the scalability limits in terms of performance and power are being reached, alternative computing paradigms with collocated computation and storage are actively being sought. A fascinating such approach is that of computational memory where the physics of nanoscale memory devices are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. We present an experimental demonstration using one million phase change memory devices organized to perform a high-level computational primitive by exploiting the crystallization dynamics. Its result is imprinted in the conductance states of the memory devices. The results of using such a computational memory for processing real-world data sets show that this co-existence of computation and storage at the nanometer scale could enable ultra-dense, low-power, and massively-parallel computing systems.

Metal Halide Perovskites: A Strategy to Design High‐Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials (Adv. Mater. 29/2017)

In article number 1701048, Jang-Sik Lee and Bohee Hwang report an approach for designing high density memory devices utilizing organolead halide perovskite (OHP) materials with a cross-point array structure which is deposited by sequential vapor deposition. The OHP-based nanoscale memory devices exhibit remarkably fast switching speed, low operating voltage, and long data retention. OHPs which are a key material in solar cells have a great potential to be used in high-density information storage devices.

Azurin/CdSe-ZnS-Based Bio-Nano Hybrid Structure for Nanoscale Resistive Memory Device.

In the present study, we propose a method for bio-nano hybrid formation by coupling a redox metalloprotein, Azurin, with CdSe-ZnS quantum dot for the development of a nanoscale resistive memory device. The covalent interaction between the two nanomaterials enables a strong and effective binding to form an azurin/CdSe-ZnS hybrid, and also enabled better controllability to couple with electrodes to examine the memory function properties. Morphological and optical properties were performed to confirm both hybrid formations and also their individual components. Current-Voltage (I–V) measurements on the hybrid nanostructures exhibited bistable current levels towards the memory function device, that and those characteristics were unnoticeable on individual nanomaterials. The hybrids showed good retention characteristics with high stability and durability, which is a promising feature for future nanoscale memory devices.

Nanoscale superconducting memory based on the kinetic inductance of asymmetric nanowire loops

The demand for low-dissipation nanoscale memory devices is as strong as ever. As Moore’s law is staggering, and the demand for a low-power-consuming supercomputer is high, the goal of making information processing circuits out of superconductors is one of the central goals of modern technology and physics. So far, digital superconducting circuits could not demonstrate their immense potential. One important reason for this is that a dense superconducting memory technology is not yet available. Miniaturization of traditional superconducting quantum interference devices is difficult below a few micrometers because their operation relies on the geometric inductance of the superconducting loop. Magnetic memories do allow nanometer-scale miniaturization, but they are not purely superconducting (Baek et al 2014 Nat. Commun. 5 3888). Our approach is to make nanometer scale memory cells based on the kinetic inductance (and not geometric inductance) of superconducting nanowire loops, which have already shown many fascinating properties (Aprili 2006 Nat. Nanotechnol. 1 15; Hopkins et al 2005 Science 308 1762). This allows much smaller devices and naturally eliminates magnetic-field cross-talk. We demonstrate that the vorticity, i.e., the winding number of the order parameter, of a closed superconducting loop can be used for realizing a nanoscale nonvolatile memory device. We demonstrate how to alter the vorticity in a controlled fashion by applying calibrated current pulses. A reliable read-out of the memory is also demonstrated. We present arguments that such memory can be developed to operate without energy dissipation.

A Strategy to Design High-Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials.

The demand for high memory density has increased due to increasing needs of information storage, such as big data processing and the Internet of Things. Organic-inorganic perovskite materials that show nonvolatile resistive switching memory properties have potential applications as the resistive switching layer for next-generation memory devices, but, for practical applications, these materials should be utilized in high-density data-storage devices. Here, nanoscale memory devices are fabricated by sequential vapor deposition of organolead halide perovskite (OHP) CH3 NH3 PbI3 layers on wafers perforated with 250 nm via-holes. These devices have bipolar resistive switching properties, and show low-voltage operation, fast switching speed (200 ns), good endurance, and data-retention time >105 s. Moreover, the use of sequential vapor deposition is extended to deposit CH3 NH3 PbI3 as the memory element in a cross-point array structure. This method to fabricate high-density memory devices could be used for memory cells that occupy large areas, and to overcome the scaling limit of existing methods; it also presents a way to use OHPs to increase memory storage capacity.

Bipolar resistive switching memory behaviors of the micro-size composite particles

Composite particles (CPs) with an average diameter of 100μm, containing the amorphous silicates, but crystal structures are dominated by the NaS2, Al2S3, Al0.55Mo2S4 and MoO3, are synthesized using hydrothermal method. Bipolar resistive switching (RS) memory behaviors with favorable resistance ON/OFF ratio, high retention and voltage cycling endurance performance are observed in the CPs-based device. The RS memory behaviors can be well controlled by stressing visible light at room temperature. The traps/deep traps based physical modes are proposed to interpret the RS memory behaviors for the quasi-bulk silicate-based composites. Different from conventional nano-scale RS memory device, the discovery of the RS memory behavior of micro-scale silicate composites may provide one new insight into the mechanism of resistive switching behavior.

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

Thermoelectric and Magnetic Properties of Sn1−x O2:Mn0.5x Co0.5x Nanoparticles Produced by the Microwave Technique

Nanoparticles (NPs) of Sn1−xO2:Mn0.5xCo0.5x with x = 0.02, 0.04, 0.06, 0.08 and 0.1 were synthesized by the microwave-assisted route and characterized for their thermoelectric and magnetic properties. As a result of Mn and Co co-doping, a considerable increase in the values of energy band gap and lattice constant c of Sn1−xO2:Mn0.5xCo0.5x NPs was observed. The x-ray photoelectron spectroscopy spectra revealed that Mn and Co ions were incorporated in their 4+ and 2+ states, respectively. The resistivity and calculated activation energy of these NPs were found to decrease by increasing the Mn and Co contents. A negative Seebeck coefficient was observed, whose value was found to be significantly increased by increasing the value of x. The magnetic measurement results revealed that all the microwave-synthesized Sn1−xO2:Mn0.5xCo0.5x NPs including the pure SnO2 have distinctly wide hysteresis loops. This indicates that samples have room-temperature ferromagnetism. The optimum value for x to have maximum saturation magnetism was observed to be 0.04. Diamagnetic contributions from the core of these NPs were noticed at higher magnetic fields. The observed magnetism was attributed to the presence of defects at the NPs' interfacing sites, grain boundaries, atom vacancies and an optimum level of Mn and Co co-dopants. The observed wide hysteresis loops in these NPs might be useful for producing nanoscale magnets and magnetic memory devices. Moreover, the observed thermoelectric properties, i.e. Seebeck coefficient and power factor in these NPs, might be useful for the development of thermoelectric devices.