Nanoscale Complementary Metal Oxide Semiconductor Research Articles

Bias dependence in statistical random telegraph noise analysis based on nanoscale CMOS ring oscillators

Random Telegraph Noise (RTN) is one of the major reliability concerns in nanoscale complementary metal-oxide semiconductor (CMOS) technologies. In this paper, we discuss the characterization of RTN in 40 nm CMOS technology using Ring Oscillators (ROSCs). We used different types of ROSCs to study the temporal and spectral characteristics of the RTN. We conducted measurements on one of the arrays with 128 identical ROSC cells. These results enabled statistical characterization of the RTN amplitude strength and its frequency characteristics in different supply voltage variations from 0.5 V to 0.7 V. At power supply of 0.65 V, dominant and observable RTN amplitude above 0.37% Δf/fmean\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\Delta f/f_{\ ext{mean}}$$\\end{document} is found in 60% of cells in the array. Further, the capture and emission time constant τe//c\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ au_{e//c}$$\\end{document} can be extracted from the measurements, the values observed ranging from 0.2 μ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\upmu$$\\end{document}s to 10 ms.

Enhanced analog/RF performance of hybrid charge plasma based junctionless C-FinFET amplifiers at 10 nm technology node

We report a novel hybrid complementary metal-oxide semiconductor (CMOS) amplifier (H-CA) combining charge plasma based junctionless (CP) n-FinFET and conventional junctionless (JL) p-FinFET and compare its analog/RF performance with JL FinFETs at 10-nm technology node. The CP FinFETs are found to exhibit improved unity gain cut-off frequency (FT) and transconductance frequency product (TFP) compared to JL FinFETs. To evaluate the performance improvement of hybrid CMOS amplifier we compare three different amplifiers, in terms of voltage gain and gain band-width. Our investigations reveal that the voltage gain of the proposed H-CA exhibits significant improvement of ∼40.02%, relative to its equally sized JL-CA value, at VBias = supply voltage (VDD)/2. Moreover, the GBW of the H-CA exhibits ∼41.67% enhancement evaluated at VBias = VDD/2 alongside showing better stability to variation in bias voltage compared to its JL counterpart. Thus CP based nanoscale CMOS amplifiers could be used for future high performance analog/RF applications.

Multiscale simulation analysis of passive and active micro/nanoelectrodes for CMOS-based in vitro neural sensing devices.

Neuron and neural network studies are remarkably fostered by novel stimulation and recording systems, which often make use of biochips fabricated with advanced electronic technologies and, notably, micro- and nanoscale complementary metal-oxide semiconductor (CMOS). Models of the transduction mechanisms involved in the sensor and recording of the neuron activity are useful to optimize the sensing device architecture and its coupling to the readout circuits, as well as to interpret the measured data. Starting with an overview of recently published integrated active and passive micro/nanoelectrode sensing devices for in vitro studies fabricated with modern (CMOS-based) micro-nano technology, this paper presents a mixed-mode device-circuit numerical-analytical multiscale and multiphysics simulation methodology to describe the neuron-sensor coupling, suitable to derive useful design guidelines. A few representative structures and coupling conditions are analysed in more detail in terms of the most relevant electrical figures of merit including signal-to-noise ratio. This article is part of the theme issue 'Advanced neurotechnologies: translating innovation for health and well-being'.

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits

Soft errors, aging effects and process variations have become the three most critical reliabil-ity issues for nanoscale complementary metal oxide semiconductor (CMOS) circuits. In this paper, the effects of bias temperature instability (BTI) and process variations on the threshold voltage of MOS devices are theoretically deduced, and the drift of the threshold voltage under the synergistic effect of BTI and process variations is analyzed. Based on the deduced threshold voltage drift formula under the synergistic effect, the critical charge and delay of different logic gates under different aging times in NanGate’s 45 nm process are simulated and analyzed. A method based on the change in the critical charge and delay of the soft error rate (SER) calculation considering BTI effect and process variations is given, and the effective-ness of our method comprehensively demonstrated using the ISCAS85,89 benchmarks. As a result, we can observe that the effect of only considering the BTI effect on the critical charge of the circuit is smaller than that of considering both the BTI effect and process variations. The simulation results show that with in-creasing aging time, the synergistic effect of BTI and process variations makes the increase in the soft error rate more serious than the impact of either effect alone.

Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware.

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

Systematic circuit design and analysis using generalised g m / I D functions of MOS devices

The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational-transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

Using well-calibrated device simulation, the analogue performance of 20 nm double-gate junctionless transistors (JLTs) is investigated in terms of transconductance (g m), output conductance (g d) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1–6 nm on both source (L S) and drain sides (L D) while keeping their sum fixed at 12 nm. Obtained results show that for both n- and p-metal-oxide-semiconductor field-effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal–oxide–semiconductor (CMOS) amplifiers featuring both n and p transistors with L S = 11 nm, L D = 1 nm and k = 80 and L S = 1 nm, L D = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs.

Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect

Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single-finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small-signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage (I–V) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller-compensated two-stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post-layout simulations were performed using standard UMC 65 nm CMOS technology.

A Hybrid CMOS-Memristor Neuromorphic Synapse.

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as [Formula: see text] in a [Formula: see text] process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.

LCNT-an approach to minimize leakage power in CMOS integrated circuits

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Radiation-induced single event upsets (SEUs), or soft errors, have become a dominant factor in the reliability degradation of nanoscale memories. In this paper, based on the SEU physics mechanism, and reasonable layout-topology, a novel soft error hardened memory cell is proposed in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design comparisons for several hardened memory cells in terms of access time (read access time and write access time), power consumption, and layout area are also executed. The main advantage of the proposed cell is that it can provide 100% fault tolerance, which is very useful for memory applications in severe radiation environments. Furthermore, Monte Carlo simulations are carried out to evaluate the effects of process, voltage, and temperature (PVT) variations. From simulations, we confirmed that the proposed cell has exhibited a sufficient multiple-node upset tolerance capability even under PVT variations.

Digital in‐situ biasing technique

A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (CMOS) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced CMOS process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm CMOS process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.

Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology

In this letter, the characteristics of metal gate (MG) fuses in 28-nm complementary metal-oxide-semiconductor (CMOS) technology are investigated. Through analyzing its initial and after program characteristics, the fuse burning process is studied. The stacked layer MG fuses exhibit two stages in the burning process. These unique programming characteristics of the MG electronic fuse provide insights for the future development low power and high reliable electrically programmable fuses by advanced nanoscale CMOS technologies.

Nanoscale CMOSFET performance improvement and reliability study for local strain techniques

In this paper, we report the investigation on a nanoscale complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) fabricated by local strained channel techniques with epitaxial silicon–germanium (SiGe) and high mechanical stress SiN as contact etch stop layer (CESL). By integrating the SiGe layer with compressive stress and the SiN film with compressive and tensile strain, both PMOS and NMOS have better drain-to-source saturation current (Isat). For short channel effect, strain scheme also show beneficial results based on Vt-roll off performance. Furthermore when capping a strained tensile film, the interface trap density for NMOS could lower down 32% comparing to control Si from charge pumping current measurement which can indicate more stable initial gate oxide quality for NMOS. The impact of these stressor schemes on device reliability, such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) have been studied to conclude that the hydrogen from compressive SiN is the key for reliability performance.

Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution

In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.

Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dBis −36 dBm.