Nanocrystal Memory Research Articles

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high- k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si 3N 4) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high- k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high- k AlN films with SiO 2 as a blocking oxide in p-Si/SiO 2/AlN/SiO 2/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.

Evaluation of HfAlO high- k materials for control dielectric applications in non-volatile memories

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high- k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO 2/HfAlO/SiO 2 triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler–Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high- k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.

Dynamical modeling of transport in MOS structures containing silicon nanocrystals for memory applications

A compact model that can be used to reproduce both quasi-static and dynamic characteristics of basic MOS cells with embedded Si-nc is presented. The structure is modeled through a device-like complex matrix of tunnel junctions, resulting in a time-dependent non-linear system of differential equations that is numerically solved, including calculation of the capacitance matrix, analytical tunneling expressions (direct and Fowler–Nordheim) for electrons/holes, and derivation of the effective tunneling area. The threshold evolution is calculated by monitoring the charge at each Si-nc as a function of time. The model is successfully validated against experimental data, showing its applicability to predict program/erase characteristics of nanocrystal memories as well as threshold voltage bit-to-bit dispersion as a consequence of geometrical non-uniformities in the nanocrystal layer position and/or gate areal coverage.

Nanoscale (EOT = 5.6 nm) nonvolatile memory characteristics usingn-Si/SiO2/HfAlO nanocrystal/Al2O3/Pt capacitors

The charge storage characteristics of thehigh-κ HfAlO nanocrystal memory capacitors prepared by atomic layer deposition in ann-Si/SiO2/HfAlO/Al2O3/Pt structure have been investigated after high-temperature annealing treatment. Thehigh-resolution transmission electron microscopy image shows that the diameter ofhigh-κ HfAlOnanocrystal is<2 nm. The high-κ HfAlO nanocrystals have been also confirmed by x-rayphotoelectron spectroscopy measurement. Due to the formation ofhigh-κ HfAlO nanocrystals with the high-temperature(∼900 °C) annealing treatment, a large hysteresis memory window of 3.7 V at a sweeping gate voltage<10 V isobserved as compared to that of the as-deposited memory capacitors. A hysteresis memory window of∼1.7 V with a small sweepinggate voltage of ± 5 V is also observed. A small equivalent oxide thickness (EOT) of 5.6 nm is obtained due to thehigh-κ memory structure design. A significant memory window ofΔV≈0.7 V at20 °C andΔV≈0.6 V at85 °C is observedafter 104 s of retention time, due to the charge confinement in thehigh-κ HfAlO nanocrystals.

Programming Speed Enhancement by NH3 Plasma Nitridation of Tunneling Oxide for Ge Nanocrystals Memory

The characteristics of Ge nanocrystals charge-storage memory stacks with plasma surface treatment of the tunneling oxide layer have been studied in this paper. The tunneling silicon oxide (TO) surface was nitrided by plasma treatment, which appears to modify the bonding type of the substrate surface and enhance the nucleation sites for Ge nanocrystals. The chemical bonding depth profile of the /TO layers and the Ge nanocrystals structure were examined by X-ray photoelectron spectroscopy and transmission electron microscopy, respectively. The trap charge densities were estimated to be as high as from hysteresis loop for sweep. The nitrided interface (oxynitride) between the trapping layer and the tunneling silicon oxide has a bandgap lower than the silicon oxide, which causes an asymmetric tunneling barrier under programming and erasing conditions. An effective thinner barrier under programming bias results in enhanced programming speed due to improved carrier injection efficiency. It was also observed that the nitrided interface reduces Ge diffusion into the TO layer, which is known to result in degradation of the properties of Ge nanocrystal-based memory devices.

Enhancement of Charge-Storage Performance in Ni-Silicide Nanocrystal Devices by Thermal Annealing a Ni–Si–N Thin Film

The stored charge characteristics of Ni-silicide nanocrystals embedded in nitride formed by annealing a Ni–Si–N thin film were studied in this paper. We used X–ray photoelectron spectroscopy, leakage current density, and X-ray diffraction to offer chemical material analysis of nanocrystals with surrounding dielectric and the crystallization of nanocrystals for different thermal annealing treatments. Transmission electron microscope analyses revealed nanocrystals embedded in the nitride layer. Nonvolatile Ni–Si nanocrystal memories with annealing revealed superior electrical characteristics for charge-storage capacity and reliability compared with the memories with 300 and annealing. In addition, we used energy-band diagrams to explain the significance of surrounding dielectric for reliability.

Using different work function nanocrystal materials to improve the retention characteristics of nonvolatile memory devices

Recently, nanocrystal nonvolatile memory (NVM) devices have attracted great research interest. Taking into account the effect of work function to account for the better retention characteristics for nanocrystals with larger work function, utilizing different work functions Au, W and Si as floating gates is proposed and comparatively studied in this paper. It was found that Au nanocrystals have better retention characteristic than W and Si. The good retention characteristic of the Au nanocrystal device is due to the larger work function and it is difficult for electrons captured by Au nanocrystal to escape from them. So, the retention characteristic of the device can be improved by using larger work function nanocrystal materials.

Memory properties of a Ge nanocrystal MOS device fabricated by pulsed laser deposition

The charge–storage properties of Ge nanocrystal (Nc) memory devices with MOS structure have been studied. The Ge nanocrystals (Ncs) were prepared on a p-Si (100) matrix by means of pulsed laser deposition (PLD) combined with rapid annealing in the presence of Ar gas. The device is characteristic of better switching characteristics (the I on/I off>105), low leakage current, which was attributed to the effect of Coulomb blockade preventing injection. A significant threshold-voltage shift of 0.85 V was observed when an operating voltage of 5 V was implemented on the device. The kind of hysteresis behavior in the double sweep suggests that the device has a good electrostatic control over the Ge Nc channel.

Modeling of the charging dynamics in silicon nanocrystal nonvolatile flash memory cells

Charging dynamics of silicon nanocrystal nonvolatile flash memory cells is explained using a simplified engineering model based on effective mass approximation. The model is comprehensive with all necessary physics and includes the presence of discrete energy levels in these nanocrystals and also the effect of shift in energy levels in the nanocrystals with more than one electron. The simulated results of current versus time and current versus gate voltage match very well with the experimental results. The results explain the anomalous peaks observed in the I– V characteristics. These peaks can be attributed to the charging of the smaller diameter nanocrystals with more than one electron at higher gate voltages.

Electron programing and hole erasing in silicon nanocrystal Flash memories with fin field-effect transistor architecture

We investigated the feasibility of electron programing and hole erasing in silicon nanocrystal Flash memory cells with fin field-effect transistor architecture having ultrashort channels (90nm). Experiments show that, by choosing a proper program/erase condition, very large threshold voltage windows can be achieved, compatible with the needs of multilevel cells. These performances are coupled to excellent retention at high temperature. The obtained results evidence that hole trapping is less affected by electric field and temperature stress compared to electron trapping. Qualitative explanations for this behavior are given.

A $\hbox{TiSi}_{2}/\hbox{Si}$ Heteronanocrystal Memory Operated With Hot Carrier Injections

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The programming and erasing of a <formula formulatype="inline"><tex>$\hbox{TiSi}_{2}/\hbox{Si}$</tex> </formula> heteronanocrystal memory were carried out by channel hot electron injection and drain side hot hole injection, respectively. Compared to an Si nanocrystal memory, a <formula formulatype="inline"><tex>$\hbox{TiSi}_{2}/\hbox{Si}$</tex> </formula> heteronanocrystal memory exhibits much better writing/erasing efficiency and higher writing/erasing saturation level. The retention transient process indicates that the <formula formulatype="inline"><tex>$\hbox{TiSi}_{2}/\hbox{Si}$</tex> </formula> heteronanocrystal memory has a very slow charge loss mechanism. The result of the localization of charge shows that a reverse read leads to a higher threshold voltage shift, which is almost not dependent on the amplitude of the read voltages. </para>

Reliability characteristics of NiSi nanocrystals embedded in oxide and nitride layers for nonvolatile memory application

The authors provided the reliability characteristics of nonvolatile nickel-silicide nanocrystal memories embedded in oxide and nitride layers for next-generation nonvolatile memory application. The charge trapping layer was deposited by sputtering a commixed target in the argon and oxygen/nitrogen ambiances, and then using a low temperature rapid thermal annealing to form nanocrystals. Transmission electron microscope clearly shows the sharpness and the density of nanocrystals. These proposed memory structures were compared for the charge storage ability, retention, and endurance. In addition, we used a simple simulation of electric field for nonvolatile nanocrystals memory to explain the advantages by using the high-k dielectric.

Nonvolatile memory with molecule-engineered tunneling barriers

We report a novel field-sensitive tunneling barrier by embedding C60 in SiO2 for nonvolatile memory applications. C60 is a better choice than ultrasmall nanocrystals due to its monodispersion. Moreover, C60 provides accessible energy levels to prompt resonant tunneling through SiO2 at high fields. However, this process is quenched at low fields due to highest occupied molecular orbital (HOMO)-lowest unoccupied molecular orbital (LUMO) gap and large charging energy of C60. Furthermore, we demonstrate an improvement of more than an order of magnitude in retention to program/erase time ratio for a metal nanocrystal memory. This shows promise of engineering tunnel dielectrics by integrating molecules in the future hybrid molecular-silicon electronics.

Physical and Electrical Properties of High-k PrTixOy Nanocrystal Memories

We proposed a high- metal-oxide insulator oxide-silicon-type structure with a nanocrystal layer grown on the tunneling oxide of a memory device using reactive radio frequency sputtering. We found that the nanocrystal film annealed at exhibited a large memory window of 3.2 V in the capacitance–voltage curve and good data retention up to (only a 5 and 10% charge loss at 25 and , respectively) due to deep trapping in the layer. This phenomenon is attributed to a well-crystallized structure and the decrease of the Pr-silicate thickness observed by X-ray diffraction and X-ray photoelectron spectroscopy, respectively.

Readout drain current dependence of programming window in nanocrystal memory cells

The different behaviour of nanocrystal memory cells in linear and subthreshold region was studied. It was found that the programming window reduces with increasing readout drain current. This peculiar behaviour derives from the presence of the discrete nanodots and it has not been observed in conventional floating gate memories.

Light-induced programming of Si nanocrystal flash memories

We show theoretically that it is possible to achieve much faster programming performances in nanocrystal flash memory devices by means of a light-induced mechanism that inverts the direction of charge transfer between nanocrystals and device substrate in comparison to conventional voltage-induced programming. Our method is based on the self-consistent solutions of Hartree and Poisson equation for both electrons and holes with open boundary conditions.

Silicon nano-particles in SiO2 sol–gel film for nano-crystal memory device applications

A novel 2-bit nano-silicon based non-volatile memory is proposed to double memory density. The thin film structure exhibits two conduction states (ON and OFF) at different voltages and has a cost-effective structure. The structure utilizes the good electrical properties of fluorinated SiO2 thin films, together with the bi-stable properties conferred by the nano-silicon particles therein embedded. A polymeric layer of 8-hydroxyquinoline aluminum salt (Alq3) further deposited on the top of the nano-particle layer through chemical evaporation and a silver paste contact determines the final structure. The positive 0–15V scan reveals two discontinuities with an ON/OFF ratio of 104–105 (2–4V) and OFF/ON of 103 (12.5–13.0V). The reverse scan displays again two distinct thresholds, range of 10.5–11.0V (ON/OFF ratio 10−3), respectively, 0.5V (OFF/ON ratio 10−5–10−4).

Modeling of programming time of nanocrystal flash memory cells

Charging dynamics of nanocrystals in the emerging silicon nanocrystals-based flash memory is explained using a simplified engineering model based on effective mass approximation. The model includes the presence of discrete energy levels in the nanocrystals and also the effect of shift in energy levels in the nanocrystals with more than one electron. The simulated results of shift in threshold voltage as a function of programming time, and the effect of gate voltage and drain voltage on the programming speed agree very well with the experimental results. The tunnel mass of electron in the oxide, which is used as a fit parameter, takes into account the effect of strain and crystallographic orientational effects. Assumptions and limitations of the model are discussed.

Nonvolatile memory characteristics influenced by the different crystallization of Ni–Si and Ni–N nanocrystals

The formation of Ni–Si and Ni–N nanocrystals by sputtering a Ni0.3Si0.7 target in argon and nitrogen environment were proposed in this paper. A transmission electron microscope analysis shows the nanocrystals embedded in the nitride layer. X-ray photoelectron spectroscopy and x-ray diffraction also offer the chemical material analysis of nanocrystals with surrounding dielectric and the crystallization of nanocrystals for different thermal annealing treatments. Nonvolatile Ni–Si nanocrystal memories reveal superior electrical characteristics for charge storage capacity and reliability due to the improvement of thermal annealing treatment. In addition, we used energy band diagrams to explain the significance of surrounding dielectric for reliability.

Comparison of electron and hole charge-discharge dynamics in germanium nanocrystal flash memories

Electron and hole charge and discharge dynamics are studied on plasma enhanced chemical vapor deposition grown metal-oxide-silicon germanium nanocrystal flash memory devices. Electron and hole charge and discharge currents are observed to differ significantly and depend on annealing conditions chosen for the formation of nanocrystals. At low annealing temperatures, holes are seen to charge slower but to escape faster than electrons. They discharge slower than electrons when annealing temperatures are raised. The results suggest that discharge currents are dominated by the interface layer acting as a quantum well for holes and by direct tunneling for elec-trons.