NAND Gates Research Articles

Large-scale and stacked transfer of bilayers MoS2 devices on a flexible polyimide substrate

Two-dimensional transition metal dichalcogenides (TMDs), as flexible and stretchable materials, have attracted considerable attention in the field of novel flexible electronics due to their excellent mechanical, optical, and electronic properties. Among the various TMD materials, atomically thin MoS2 has become the most widely used material due to its advantageous properties, such as its adjustable bandgap, excellent performance, and ease of preparation. In this work, we demonstrated the practicality of a stacked wafer-scale two-layer MoS2 film obtained by transferring multiple single-layer films grown using chemical vapor deposition. The MoS2 field-effect transistor cell had a top-gated device structure with a (PI) film as the substrate, which exhibited a high on/off ratio (108), large average mobility (∼8.56 cm2 V−1 s−1), and exceptional uniformity. Furthermore, a range of flexible integrated logic devices, including inverters, NOR gates, and NAND gates, were successfully implemented via traditional lithography. These results highlight the immense potential of TMD materials, particularly MoS2, in enabling advanced flexible electronic and optoelectronic devices, which pave the way for transformative applications in future-generation electronics.

The accuracy analysis of different algorithms for 4-Bit absolute value detector

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

Toward a Voltage Reconfigurable Logic Gate

Currently, novel approaches are being developed to overcome the imminent Moore's law failure. The techniques attempt to gain greater computing power by reducing the number of transistors. This work presents the simulation of a reconfigurable voltage logic gate based on the equation of a plane. The proposal is achieved by using two variables of the equation of a plane as inputs and the other as output. The proposed circuit can perform the NAND and NOR logic gates, known as universal logic gates. The simulation results show the feasibility of the proposed reconfigurable logic gate. Also, the presented circuit is compatible with the transistor-transistor-logic and can be modified to implement other logic gates by changing a voltage level.

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

Electronic Devices Made from Chitin: NAND Gates Made from Chitin Sorbates and Unsaturated Bridging Ligands—Possible Integration Levels and Kinetics of Operation

Chitin (usually derived from aq. arthropods like shrimp Pandalus borealis) acts as a potent metal sorbent in both environmental monitoring and retention applications such as wastewater purification or nuclear fuel reprocessing. Given this established (starting in the 1970s) use of chitin and the fact that adsorption of metal ions/complexes to chitin does increase the currents observed in metal-centered redox couples by a factor of about 10, it is straightforward to conceive self-organized (by adsorption modified by adding certain ligands bridging M and chitin) surface films which exert electrical information processing by means of inner-sphere redox processes. Preliminary work is shown concerning the influence of ligands—including some possibly acting as inner-sphere-transfer agents, like caffeic acid—on metal ion retention by chitin. Another ligand is reported to enhance current flow into electrodes (i.e., electron injection from some reducing cation). These inner-sphere redox processes, in turn, can be controlled by creating or removing a chain of conjugated double bonds, e.g., by Diels–Alder reactions. Devices admitting corresponding reagents in a controlled manner and appropriate array then act as NAND gates, thus being components capable of performing each kind of classical computation. Applications in environmental analysis and “green” computing for simple purposes like electronic keys are suggested. The empirical basis for these conclusions includes studies on the influences of ligand additions on M adsorption (Mn, Ni, several REEs…) on chitin; some of these bridging ligands, like caffeinate and ferulate, can reversibly react with appropriate dienes. At the employed concentrations, distances among adsorbed metal ions are 1–3 nm, meaning that the charge-flow control takes spacer ligands like carotenoids. Practical setups are pointed to, using evidence from ligand-augmented metal ion–chitin interactions, which might combine oxidizing (Ce) and optically address reducing (Eu) metal ions into a framework for coligand-controlled charge flow.

Ultra-broadband and ultra-compact chip-integrated logic gates based on an inverse design method

The Si-based chip-integrated OR, XOR, NOR, AND and NAND all-optical logic gates (AO-LGs) with footprints of 2 μm × 2 μm are inversely designed based on an intelligent method, which combines the method of moving asymptotes (MMA) with the finite element method (FEM). In this method, the substrate is divided into many small units, and the refractive index of each unit will be perturbed according to design expectation. Therefore, the optimized refractive index will be gradient, which divorces from fabrication. Binary reconstruction is the process of changing the gradient media into binary media, by filtering out the gradient virtual media, smoothing the boundaries, and refilling Si or air on the substrate to form a new structure. Numerical simulations demonstrate that all the AO-LGs designed by this method work effectively. The contrast ratio (CR) of OR/XOR gate ranges from 23.50 dB to 25.50 dB, NOR gate ranges from 6.33 dB to 7.91 dB, AND gate ranges from 4.44 dB to 6.13 dB, and NAND gate ranges from 8.85 dB to 10.07 dB. And these designed AO-LGs achieve nearly ten times more broad bandwidth than the other reported conventional gates without suffering other performances too much. The OR/XOR, and NOR gate functions well in a broad band range from 800 nm to 1600 nm, and from 850 nm to 1350 nm. AND gate functions well from 1000 nm to 1240 nm and from 1310 nm to 1400 nm. NAND gate functions well from 1360 nm to 1530 nm. It is expected that such a robust method can serve extensive applications in designing photonic devices, and the compact logic gates may contribute to broad applications of future optical computing and signal processing.

Efficient and low-cost approximate multipliers for image processing applications

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works.

Retracted: Visual Construction of Logical AND and NAND Gates

Retracted: Visual Construction of Logical AND and NAND Gates

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments.

High‐Speed Operation of Electrochemical Logic Circuits Depending on 3D Construction of Transistor Architectures

AbstractThe emergence of organic electrochemical transistors (OECTs) has opened a new era of printable electronics and bioelectronics, due to their unique advantages including innately superior transconductance and biocompatibility. Despite the foreseeable advancements available from their further implementations in fundamental logic circuitry, however, insufficient operation speeds and short compatibilities to scaling‐down have so far hindered advanced integrations other than biosensing and biosignal amplifications. Here, a 3D‐construction‐dependent operational analysis of OECTs is reported, with which an all‐vertical architectural design enabled unprecedentedly high operating speed and a facile expansion to large‐area and high‐density 3D crossbar arrays. A simple vertical channel architecture completed with solid‐state Ag/AgCl top‐gate electrodes enables an ultrafast redistribution of ions within channels, yielding a state‐of‐the‐art operation frequency reaching 12 MHz V−1. Various printed logic circuit arrays, including NOT, NAND, and NOR gates, with high stability and reproducibility.

A unique universal block in QCA technology

The limitations of Complementary Metal Oxide Semiconductor (CMOS) such as high-power dissipation, short channel effects, and high lithography has prompted scientists to look forward to alternatives. Many nanotechnologies were emerged and still in the competition such as Fin Field-Effect Transistor (FinFET), Carbon Nanotube Field-Effect Transistor (CNFET), Quantum-dot Cellular Automata (QCA). QCA is a new nanoelectronics technology used a new method for calculations and it is a promising technology in terms of power dissipation. In QCA, circuit complexity is depending on cell count, area and latency. For commercial purposes a universal gate is necessary, this gate can be used alone to design any Boolean function, where in CMOS technology, the NAND or NOT gates have the ability to be a universal gate. The dominant gates in QCA are the majority gate with inverter where QCA circuits cannot be designed using only a universal gate. Because the structure of the gate is important in QCA, this paper introduces a new low complexity singular block that can be used as a universal block. The proposed block can be used to form AND, OR, NOT, Exclusive-OR (XOR) and Multiplexer (MUX). So, this block not just used to design any circuit but also it can be used to form other important functions XOR and MUX to build large circuits in an optimum form.

DCDRO:A true random number generator based on dynamically configurable dual-output ring oscillator

As an essential component of modern encryption systems, a true random number generator (TRNG) has made significant contributions to information security. A configurable true random number generator with low hardware overhead and high throughput is presented in this paper. The structure utilizes an odd number of NAND gates and XOR gates to create a dynamically configurable dual-output ring oscillator. By increasing the phase noise in a short period, the time jitter range is expanded, thereby improving the randomness of the entropy source. Additionally, the XOR post-processing reduces the bias of the random sequence. The structure has undergone several tests and validations on the Xilinx Kintex-7, and the experimental results demonstrate that the proposed TRNG has strong robustness under varying environmental conditions, including different temperatures (0 °C–80 °C) and output voltages (0.8 V–1.2 V). It only consumes 28 LUTS and 5 DFFs in hardware resources and achieves a throughput of up to 200 Mb/s.

Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.

High-Temperature-Operable Electromechanical Computing Units Enabled by Aligned Carbon Nanotube Arrays.

Nano/micro-electromechanical (NEM/MEM) contact switches have great potential as energy-efficient and high-temperature-operable computing units to surmount those limitations of transistors. However, despite recent advances, the high-temperature operation of the mechanical switch is not fully stable nor repetitive due to the melting and softening of the contact material in the mechanical switch. Herein, MEM switches with carbon nanotube (CNT) arrays capable of operating at high temperatures are presented. In addition to the excellent thermal stability of CNT arrays, the absence of a melting point of CNTs allows the proposed switches to operate successfully at up to 550 °C, surpassing the maximum operating temperatures of state-of-the-art mechanical switches. The switches with CNTs also show a highly reliable contact lifetime of over 1 million cycles, even at a high temperature of 550 °C. Moreover, symmetrical pairs of normally open and normally closed MEM switches, whose interfaces are initially in contact and separated, respectively, are introduced. Consequently, the complementary inverters and logic gates operating at high temperatures can be easily configured such as NOT, NOR, and NAND gates. These switches and logic gates reveal the possibility for developing low-power, high-performance integrated circuits for high-temperature operations.

Investigations of all-optical gates based on linear photonic crystals using the PSK technique and beam interference effect

ABSTRACT In this paper, all optical OR, AND, NOR and NAND gates based on linear photonic crystals (LPhCs) have been numerically designed and simulated by the plane wave expansion (PWE) and finite difference time domain (FDTD) methods. The LPhC fundamental structure with cross-section of 114 is used for designing the proposed all optical gates (AOGATEs), which is composed of 15 × 23 cubic matrix of dielectric silicon rods in air substrate. The mechanism of the proposed AOGATEs is performed based on phase shift keying (PSK) technique and beam interference effect. Simulation results by FDTD approach illustrate the minimum contrast ratio of 8.88 and 10.31 dB for all optical AND/NOR and OR/NAND logic gates, respectively. Also, the minimum bit rate is obtained as 3.34 Tb/s for AND/NOR and 5 Tb/s for OR/NAND logic gates.

Simulation and Numerical Analysis of SOA Based All Optical NAND Gate for High Data Rate Communication

As a result of the development of advanced semiconductor-based optical switching devices and their commercialization, concepts and technologies in all-optical signal processing have evolved significantly in the past few years. In order to realize logical operations in photonic computing, universal gates are needed. In this research, the simple and compact all-optical NAND gate was designed using SOA and simulated at a high data rate of 10Gbps to 40 Gbps. The performance of the proposed NAND gate is shown by the numerical analysis for various input combinations and SOA. By changing wavelengths, injection currents, confinement factors, as well as optical components such as sources, amplifiers, and filters, a numerical analysis is performed. Unique results were obtained at a 10 Gbps data rate for NRZ-L user-defined bit sequences. This kind of all-optical NAND gate will be the perfect alternative in the field of optical computing to realize a high-speed optical communication network. An extinction ratio of 11.48 dB is achieved at a high-speed data rate of 10 Gbps to 40Gbps. The output spectrum of the designed NAND logic is also received for a wide input spectrum and the system responds selectively for the input wavelength at 1548.3 nm which is the probe signal wavelength.

Study of Ionization Radiation Effects in Digital Circuits for Aerospace Application

Combinational standard cells based on the RHBD approach and using 180 nm technology with Cadence Virtuoso are the focus of this work effort. Radiation from space, heavy ions, and radioactive particles (protons, neutrons) pose the greatest threat to integrated circuits (ICs).Single Event Transients (SETs), a serious issue for digital semiconductor design, are caused by ever reduced feature sizes and declining supply voltage. The three proposed C-element based cells under investigation are inverter, NAND gate, and buffer. The Cadence Virtuoso programme was used to create their schematics. RHBD-based circuit designs are more tolerant of Single Event Effects (SEE), better at resisting noise, and consume less static power. Less static power is used in RHBD-based circuit designs, which also have better noise resistance. For the other C-element-based logic circuits, the Noise Margin is likewise enhanced in comparison to the comparable conventional circuits.

기울기 기반 허프 변환을 이용한 실시간 차선 검출 시스템 설계

Straight line detection using the gradient-based Hough transform has high accuracy, but has the disadvantage of increased memory and longer processing time due to storing and processing a lot of data. The proposed architecture applies the gradient-based Hough transform algorithm to consider only the points in the range of -4 to +4 centered on the gradient angle in parallel, and increases accuracy by applying the highest weight to the central pixel. In order to improve overall performance, the LUT for the trigonometric functions and voting memory for weight values are divided into 9 parts for each address area, so that the line detection speed is improved by processing data at the same time. The proposed architecture was designed with VerilogHDL and synthesized with DBhitek 110nm standard cell library and the results showed that the maximum operating frequency was 210Mhz (73 fps) with 15K of 2-input NAND gates and 5,950Kb of memory.