Abstract

Combinational standard cells based on the RHBD approach and using 180 nm technology with Cadence Virtuoso are the focus of this work effort. Radiation from space, heavy ions, and radioactive particles (protons, neutrons) pose the greatest threat to integrated circuits (ICs).Single Event Transients (SETs), a serious issue for digital semiconductor design, are caused by ever reduced feature sizes and declining supply voltage. The three proposed C-element based cells under investigation are inverter, NAND gate, and buffer. The Cadence Virtuoso programme was used to create their schematics. RHBD-based circuit designs are more tolerant of Single Event Effects (SEE), better at resisting noise, and consume less static power. Less static power is used in RHBD-based circuit designs, which also have better noise resistance. For the other C-element-based logic circuits, the Noise Margin is likewise enhanced in comparison to the comparable conventional circuits.

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