NAND Devices Research Articles

낸드 플래시 기반 저장장치의 피크 전류 모델링을 이용한 전력 최적화 기법 연구

낸드플래시 기반 저장장치는 성능 향상을 위해 다중 채널, 다중 웨이 구조를 통해 다수의 낸드 디바이스를 병렬 동작시키고 있다. 하지만 동시 동작하는 낸드 디바이스의 수가 늘어나면서 전력 소모 문제가 가시화되었으며, 특히 디바이스 간 복수의 피크 전류가 서로 중첩되면서 높은 전력소모로 인해 데이터 신뢰성과 시스템 안정성에 큰 영향을 미치고 있다. 본 논문에서는 낸드 디바이스에서 지우기, 쓰기, 읽기 동작에 대한 전류 파형을 측정, 이를 프로파일링하여 피크 전류에 대한 정의와 모델링을 진행하였고, 나아가 다수의 낸드에서 피크 전류 중첩 확률을 계산한다. 또한 시스템 수준의 TLM 시뮬레이터를 개발하여 다양한 시뮬레이션 시나리오를 주입하여 피크 전류 중첩 현상을 분석 한다. 본 실험 결과에서는 낸드간 피크 중첩 현상을 차단할 수 있는 간단한 전력 관리 기법을 적용하여 피크 전류 중첩과 시스템 성능 간의 관계를 살펴보고 이를 통해 성능 저하 최소화를 위한 피크 중첩 비율을 제시하였다. NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.

Focus on software and semiconductor equipment

Focus on software and semiconductor equipment

Impact of <inline-formula> <tex-math notation="TeX">${\hbox{V}}_{\rm pass} $</tex-math></inline-formula> Interference on Charge-Trapping NAND Flash Memory Devices

The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$C _{BL}$</tex></formula> ), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V _{THC}$</tex> </formula> ), DNSS reduces the cross-layer <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$C _{BL}$</tex></formula> -mismatch by 41%, LA-PV-R using various program-threshold-voltages ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$V _{THP}$</tex></formula> ) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V _{THP}$</tex></formula> between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.

Three-Dimensional Integration Approach to High-Density Memory Devices

The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random access memory devices. High-mobility [~μsaturation of 20 cm2/(eV·s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

The non-volatile memory market, especially the NAND market, has grown explosively in recent years and its business/market volume has become comparable to that of DRAM. NAND device technology has become a technology driver in physical dimension scaling because its structure and layout are simpler than DRAM and logic circuit. However, the current floating gate-type structure has inherent limiting factors in physical scaling. To overcome the scaling limit of floating gate NAND structures, a charge trap flash (CTF)-based structure is believed to show promise even though it still has issues, such as data retention and slow program erase, due to its unique gate stack structure. To improve erase speed and data retention, a barrier engineering (BE) approach for the tunneling layer and blocking layer/metal electrode shows promise for CTF devices. For the gate electrode, a stable, high WF solution is required. The large conduction band offset is necessary for the blocking oxide layer for better retention, but needs to be optimized in a sense of programming/erasing and retention. For the tunnel barrier, a high- k based tunnel barrier is a promising approach to improving erase speed and retention. However, reliability of tunnel oxide should be carefully studied. To determine the optimum gate stack for MANOS in terms of retention, P/E speed, and endurance, strategic approaches to improve device characteristics are required.

Susceptibility of CMOS IC Devices Under Narrow-Band High Power Electromagnetic Waves by Magnetron

We investigated the damage effects of CMOS IC devices manufactured using three different technologies under narrow-band high power electromagnetic (NB-HPEM) waves by magnetron. The output of NB-HPEM waves was controlled from 0 to 1 kW, and the narrow-band operating frequency was 2, 460±50 MHz. The NB-HPEM waves were propagated into a closed-ended standard rectangular waveguide for 1 s. During our investigation, six different semiconductor technologies (three CMOS AND, and three CMOS NAND devices) were tested. The CMOS IC devices showed two types of damage i) malfunction, which means that no physical damage occurred in the system and after a reset, the system returned to normal function, and ii) destruction, which means that the system incurred physical damage, and operation could not be recovered without hardware repair. We increased the electric field, and the HCT and HC series of CMOS AND and NAND devices underwent reversible malfunctions. Furthermore, the HCT and HC series of CMOS AND and NAND devices were not destroyed at the maximum electric field (E max = 23.938 kV/m). However, only the AC series of CMOS AND and NAND devices underwent reversible malfunctions and experienced permanent destruction at much higher fields. The surfaces of the destroyed CMOS devices were removed and the chip conditions were investigated with a microscope. The microscopic analysis of the damaged devices showed component and bondwire destruction such as breakthroughs and melting due to thermal effects. Our results are expected to provide fundamental data for interpreting the combined failure mechanism of digital IC devices in an intentional electromagnetic environment.

A Novel nand Flash Memory With Asymmetric S/D Structure Using Fringe-Field-Induced Inversion Layer

A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and improve the th distribution is presented in this paper. The asymmetric S/D structure consists of a diffused junction and inversion layer which is induced by the fringe field of the gate bias voltage during NAND operation. To reduce the area overhead caused by the select transistors, a 64-cell NAND string, which is twice the number of cells used in conventional NAND devices, is also evaluated. The proposed NAND memory device is demonstrated by a 32-Mb test chip which is fabricated using a 60-nm NAND flash technology. It exhibits subthreshold slope characteristics that improved by 37% and a programmed th distribution width that improved by 35% while almost maintaining multiple-level-cell NAND flash performance requirements.