N-channel Thin-film Transistors Research Articles

Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology.

Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported. Herein, we demonstrate for the first time that Cu-doped SnO (Cu:SnO) with HfO2 capping can be employed for high-performance p- and n-channel TFTs. The interstitial Cu+ can induce an n-doping effect while restraining electron-electron scatterings by removing conduction band minimum degeneracy. As a result, the Cu3atom%:SnO TFTs exhibit a record high electron mobility of 43.8 cm2 V-1 s-1. Meanwhile, the p-channel devices show an ultrahigh hole mobility of 2.4 cm2 V-1 s-1. Flexible complementary logics are then established, including an inverter, NAND gates, and NOR gates. Impressively, the inverter exhibits an ultrahigh gain of 302.4 and excellent operational stability and bending reliability.

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

可控掺杂双极性半导体聚合物应用于简化构筑综合 性能优异的有机逻辑电路

Organic electronics aims to simplify the construction of high-performance basic logic circuits for various applications. Ambipolar organic semiconductors, particularly ambipolar conjugated polymers, offer distinct advantages of easy solution-printing-based fabrication and low-cost development of large-area organic circuits. However, the narrow bandgaps of intrinsic ambipolar polymers result in the low current on/off ratio (generally 102–103), impeding the generation of output signals with high accuracy and immunity, which are critical requirements for potential logic circuit applications. The quasi-unipolar transport properties for pristine well-balanced ambipolar polymers were obtained using a controllable-doping process, which resulted in a significant increase in current on/off ratios (105–107) for both p-channel and n-channel thin-film transistors. Furthermore, large-area organic logic circuits such as NOT, NOR, and NAND gates were constructed using a direct writing technique based on the same ambipolar conjugated polymer films with superior p- and n-conducting channels by the controllable-doping process, demonstrating excellent overall performance with a high gain value of ∼150, signal noise margins of 68% and fast response to input voltages. This study provides valuable guidelines for improving the on/off ratio of ambipolar materials by implementing the doping strategy, further promoting the possibility of practical applications in solution-printed integrated organic circuits.

High-speed hybrid complementary ring oscillators based on solution-processed organic and amorphous metal oxide semiconductors

Solution-processed single-crystal organic semiconductors (OSCs) and amorphous metal oxide semiconductors (MOSs) are promising for high-mobility p- and n-channel thin-film transistors (TFTs), respectively. Organic−inorganic hybrid complementary circuits hence have great potential to satisfy practical requirements. However, some chemical incompatibilities between OSCs and MOSs, such as heat and chemical resistance, make it difficult to rationally integrate TFTs based on solution-processed OSC and MOS onto the same substrates. Here, we report a rational integration method based on the solution-processed semiconductors by carefully managing the device configuration and the deposition and patterning techniques from a materials point of view. The balanced high performances as well as the uniform fabrication of the TFTs led to densely integrated five-stage ring oscillators with a short propagation delay of 1.3 µs per stage.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel Thin-film-transistor (TFT) TFT materials such as ZnO, InGaZnO, AMO-CNT, and organic materials dramatically improved the achieved and projected TFT performance. The low field mobility of oxide materials has reached values comparable to those for short-channel Si CMOS. The effects related to electron inertia and electron density oscillations in field effect transistors channels (FETs) diminish the role of the low field mobility as a figure of merit in short channel devices making the performance gap between TFTs and Si CMOS smaller enabling high frequency TFT applications even reaching sub-THz and THz frequencies (for the operating regimes using the rectification of the plasma oscillations. We report on an improved compact model based on the RPI TFT model [1] and using the Unified Charge Control Model (UCCM). [2, 3] This model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. It also accommodates the inclusion of the parasitics related to the gate impedance. These new features allowed us to obtain an excellent agreement with the measured I-V/C-V characteristics for both long and short n-channel and p-channel TFTs. The application of this new TFT model to the analysis of the TFT response requires accounting for non-local potential distribution in the device channel. This is achieved by using a multi-segment nonlinear transmission line model of the TFT channel reproducing the approach that has been previously used for the THz SPICE/ADS Si CMOS model implementation. As a possible application example, we simulated a TFT complementary inverter. Our simulations showed that using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT. These results show that the TFT RFID and other applications could be extended into the THz range of frequencies.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

The excellent performance of n-channel thin film transistors (TFTs) based on amorphous oxide semiconductors has allowed integrated circuits based on NMOS logic to be successfully realized. However, future development will require CMOS logic to avoid excessive power dissipation and therefore p-channel TFTs are needed. Thin film p-type oxide semiconductors are rarely amorphous, and their microstructure has a significant impact upon both hole mobility and off-state current. In silicon MOSFETs, it is possible to scale device geometry to compensate for the lower hole mobility relative to electron mobility, but in TFTs this results in an excessive off-state current in the p-channel TFT as the off-state current also scales with geometry, which is not true to the same degree in silicon MOSFETs. Using new scaling rules that account for the off-state current, it is possible to optimize p-channel TFTs to operate alongside n-channel TFTs to achieve low power CMOS logic.

High-performance hysteresis-free perovskite transistors through anion engineering

Despite the impressive development of metal halide perovskites in diverse optoelectronics, progress on high-performance transistors employing state-of-the-art perovskite channels has been limited due to ion migration and large organic spacer isolation. Herein, we report high-performance hysteresis-free p-channel perovskite thin-film transistors (TFTs) based on methylammonium tin iodide (MASnI3) and rationalise the effects of halide (I/Br/Cl) anion engineering on film quality improvement and tin/iodine vacancy suppression, realising high hole mobilities of 20 cm2 V−1 s−1, current on/off ratios exceeding 107, and threshold voltages of 0 V along with high operational stabilities and reproducibilities. We reveal ion migration has a negligible contribution to the hysteresis of Sn-based perovskite TFTs; instead, minority carrier trapping is the primary cause. Finally, we integrate the perovskite TFTs with commercialised n-channel indium gallium zinc oxide TFTs on a single chip to construct high-gain complementary inverters, facilitating the development of halide perovskite semiconductors for printable electronics and circuits.

Modulation of vacancy-ordered double perovskite Cs2SnI6 for air-stable thin-film transistors

Vacancy-ordered halide double perovskites are promising non-toxic and stable alternatives for their lead- and tin (II)-based counterparts in electronic and optoelectronic applications. Despite extensive theoretical studies on this emerging family of materials, efforts devoted to the chemical modulation of their thin-film properties and their potential application in electronic devices remain rare. Here, we develop a facile one-step solution processing strategy to tune the film quality of cesium tin (IV) iodide (Cs 2 SnI 6 ) perovskite and demonstrate its feasibility in thin-film transistor (TFT) application. We reveal critical roles of precursor stoichiometric ratio and solvent engineering in achieving uniform and highly crystalline Cs 2 SnI 6 films with superior electron mobility. We further modulate the electronic properties by incorporating an external manganese (Mn 2+ ) dopant, achieving high-performance air-stable n-channel TFTs and all-perovskite complementary inverters. We anticipate that the present study would pave the way for expanding the environmentally friendly and stable perovskites toward widespread applications. • Precursor engineering for one-step solution deposition of Cs 2 SnI 6 thin films • Electrical modulation of the Cs 2 SnI 6 perovskite for transistor application • Integrated transistors exhibit appealing electrical performance with high stability Liu et al. report the deposition of eco-friendly vacancy-ordered double perovskite Cs 2 SnI 6 thin films using a one-step solution process. Subsequently, an external atomic doping is adopted to modulate the electrical property of the Cs 2 SnI 6 perovskite. The resulting transistors exhibit appealing electrical performance with highly stable characteristics.

Atomically Thin Tin Monoxide-Based p-Channel Thin-Film Transistor and a Low-Power Complementary Inverter.

Atomically thin oxide semiconductors are significantly expected for next-generation cost-effective, energy-efficient electronics. A high-performance p-channel oxide thin-film transistor (TFT) was developed using an atomically thin p-type tin monoxide, SnO channel with a thickness of ∼1 nm, which was grown by a vacuum-free, solvent-free, metal-liquid printing process at low temperatures, as low as 250 °C in an ambient atmosphere. By performing oxygen-vacancy defect termination for the bulk-channel and back-channel surface of the ultrathin SnO channel, the presented p-channel SnO TFT exhibited good device performances with a reasonable TFT mobility of ∼0.47 cm2 V-1 s-1, a high on/off current ratio of ∼106, low off current of <10-12 A, and a subthreshold swing of ∼2.5 V decade-1, which was improved compared with the conventional p-channel SnO TFTs. We also fabricated metal-liquid printing-based n-channel oxide TFTs such as n-channel SnO2 and In2O3-TFTs and developed ultrathin-channel oxide-TFT-based low-power complementary inverter circuits with the developed p-channel SnO TFTs. The full swing of voltage-transfer characteristics with a voltage gain of ∼10 and a power dissipation of <4 nW for p-SnO/n-SnO2 and ∼120 and <2 nW for p-SnO/n-In2O3-CMOS inverters were successfully demonstrated.

Highly Efficient Inverted Organic Light-Emitting Diodes Adopting a Self-Assembled Modification Layer.

Inverted organic light-emitting diodes (IOLEDs) can be integrated with low-cost n-channel thin-film transistors for use in active-matrix OLEDs (AMOLEDs). However, the electron injection from conventional indium tin oxide (ITO) cathode to the upper electron transport layer usually suffers from a large injection barrier. To improve the electron injection efficiency, the electron injection layers (EILs) of ZnO modified by a self-assembled monolayer arginine (Arg) were developed to construct efficient IOLEDs. ZnO/Arg EILs present an ultralow work function (WF) of 2.35 eV, which is lower than that of ZnO modified by poly(ethylenimine) (PEI) (2.77 eV). The mechanism of low WF is attributed to the generation of strong molecular dipoles and interface dipoles at the interface of ZnO/Arg. The green fluorescent IOLEDs with ZnO/Arg present a low turn-on voltage (Von) of 3.5 V and a maximum current efficiency (CEmax) of 4.5 cd/A. Especially, the device possesses a half-life of 3600 h at an initial luminance of 1700 cd/m2, which is 36 times as long as that of the IOLEDs with ZnO/PEI as EILs. Furthermore, the green phosphorescent IOLEDs show a Von of 3.5 V, a CEmax of 59.1 cd/A, and a maximum external quantum efficiency (EQEmax) of 16.8%. At a luminance of 10 000 cd/m2, the efficiency roll-off of the device is only 6.3%.

Hydrogenated n-Channel Low Temperature Polycrystalline Silicon TFTs as Ultraviolet Dosimeters

N-channel thin film transistors (TFTs) fabricated with hydrogenated low temperature polycrystalline silicon (LTPS) were exposed to ultraviolet (UV) radiation to a cumulative dose up to 16 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The effect of radiation on the electrical characteristics of the devices was monitored after the irradiation steps and in a prolonged period after irradiation. The main monitoring parameter was the threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> th</sub> ) which was found to have exponentially linear dependence on irradiation dose. This, together with obtained low fading, suggests that hydrogenated n-channel low temperature polycrystalline silicon TFTs have potential as UV radiation dosimeters. In addition, the physical mechanisms of the UV induced electrical degradation were analyzed in terms of the radiation generated traps at poly-Si grain boundary and poly-Si and gate oxide insulator (poly-Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) interface.

(Invited) P-Type Thin Film Oxide Semiconductors for Thin Film Transistor-Based CMOS Logic

The development of products, and perhaps most notably displays, which rely on thin film transistors (TFTs) has been enabled by the availability of high quality, thin film semiconducting materials. Hydrogenated amorphous silicon (a-Si:H) was the first such material to meet the demands of the display industry. Other materials have since also gained importance including polycrystalline silicon, organic semiconductors and, most recently, oxide semiconductors. In this latter case, indium gallium zinc oxide (IGZO) has been successfully commercialised at scale. However, TFT circuits using any of these materials are based on NMOS or PMOS logic rather than CMOS preventing their use where low power consumption is essential such as display driving circuits, memories or logic as it has not proved to be possible to produce n-channel and p-channel TFTs with sufficiently similar performance characteristics in one material system. In the case of the thin film silicon-based materials, this is because the hole mobility is much lower than the electron mobility, whilst in organic semiconductors it is the p-type materials that are superior to the n-type. In this paper, the situation in oxide semiconductors is considered in detail.There are several oxide semiconductors which have been used to make excellent TFTs, perhaps most notably amorphous (a-)IGZO and amorphous zinc tin oxide (a-ZTO). Both of these materials are naturally n-type as their charge neutrality level is close to the conduction band edge. As a result, it has not proved to be possible to successfully introduce sufficient acceptor-type impurities in order to stably produce a p-type behaviour in these materials; completely different p-type thin film oxide semiconductors are therefore required. Cuprous oxide (Cu2O) is one such material, and this will be used as an exemplar in this work, although alternatives such as tin oxide (SnO) and nickel oxide (NiO) have also been reported.This move to alternative material systems presents other challenges. The conduction band minimum in n-type oxides is dominated by spatially extensive and spherically symmetric metal s-shell electron orbitals, and this allows an amorphous phase to be induced by stoichiometry control of oxide semiconductor which has no grain boundaries and is highly uniform but which retains a high electron mobility. However, the valence band maximum in the p-type materials is dominated by oxygen 2p-orbitals (sometimes with metal d-orbital hybridisation is found in Cu2O) which are highly directional. This means that any attempt to introduce an amorphous microstructure would result in a significant reduction in hole mobility compared with the crystalline state (it is this effect that is responsible for a-Si:H having an electron mobility that is 1,000 times lower than its crystalline counterpart).The types of deposition techniques (most commonly sputtering) that are used to produce thin film oxide semiconductors do not permit the production of single-crystalline thin film materials; nanocrystalline microstructures are created instead. This leads to the presence of grain boundaries, which are highly problematic as they contain a high density of defect states. As a result, they act as trap sites for holes and significantly reduce carrier mobility compared with the single crystal state. Some degree of mitigation is possible by controlling grain orientation during growth, and for Cu2O it is possible to select either the (100) or (111) orientation [1]. Grain size may also be increased and boundary defects decreased after growth by annealing [2]. The result is TFTs with a significantly lower field effect mobility (typically less than 1 cm2 V–1 s–1) than is found in the n-type oxide TFTs (typically over 10 cm2 V–1 s–1). Furthermore, these defective grain boundaries can allow the accumulation of electrons in the off-state leading to much higher off-state currents than would be expected [3]. As a result the switching ratio of p-type oxide TFTs is much lower (typically less than 103) than in equivalent n-type devices (>107).Despite these limitations, it is still possible to combine p-type and n-type oxide TFTs to make CMOS logic gates, but it is important to consider carefully the application requirements and the associated compromises that must be made in circuit design.The funding for this work by the Engineering and Physical Sciences Research Council through grant numbers EP/M013650/1, EP/P027032/1 and EP/L015455/1 is gratefully acknowledged.[1] Han, S. and Flewitt, A.J., Thin Solid Films, 704, 138000 (2020)[2] Han, S., et al., Appl. Phys. Lett., 109, 173502 (2016)[3] Han, S. and Flewitt, A.J., IEEE Electron Dev. Lett., 28, 1394 (2017)

(Invited) Process Development of CMOS TFTs for Monolithic 3D-IC Applications

Three-dimensional integrated circuit (3D-IC) technology has been used for vertical integration of multi-chip or stacked process in three-dimensional space for the scaling trend of sub-1 nm technical node, in order to overcome the physical limits of electronics and materials in the semiconductor process. Among them, monolithic 3D-IC has many features that can solve the challenge of stacking 2D molds and connecting them in the third dimension. 3D-IC has many significant advantages, such as heterogeneous integration, a smaller footprint but more powerful features, lower costs, reduced power, and higher bandwidth.In this talk, process development of CMOS thin film transistor (TFT) for monolithic 3D-IC will be presented. The channel material of upper layer is the key concern for fabricating device stacked in 3-D space due to the process thermal budget. An amorphous indium gallium zinc oxide (a-IGZO) with activation temperature under 350 ℃ is regarded as the most promising transparent amorphous oxide semiconductor (TAOS) channel material for the advanced TFT device. However, the TAOS TFT is lack of p-channel device. Hence in this work, a top gate poly-Si p-channel TFT (pTFT) device was formed with tri-gate structure by using a self-aligned double patterning (SADP) process. Then, an a-IGZO n-channel TFT (nTFT) based on a bottom gate process were stacked with a monolithic architecture on the same wafer.At first, the process development and optimization of individual AOS nTFT and poly-Si pTFT were carried out. The device structure of AOS nTFT includes a 100 nm-thick TiN metal bottom-gate, 10 nm-thick HfO2 gate dielectric, and IGZO channel. On the other hand, a 100 nm-thick TiN metal top-gate, 10 nm-thick HfO2/ 1 nm-thick SiO2 gate stack, p-type JL poly-Si channel, and tri-gate structure were applied for the poly-Si pTFT. Results show that the on/off current ratio (Ion/Ioff) values of AOS nTFT and poly-Si pTFT are 7 and 6.8 orders, respectively. And the subthreshold swing (S.S.) values are135 and 128 mV/decade, respectively. The device performance of the individual n/p TFTs in this work is similar to that of state-of-the-art devices.Afterwards, hybrid CMOS inverter devices were fabricated and stacked with a monolithic 3D-IC architecture. The Ion/Ioff values of AOS nTFT and poly-Si pTFT are 7.1 and 6.3 orders, respectively. And the S.S. values are135 and 133 mV/decade, respectively. The device performance is quite similar to those of individual n/p TFT fabricated in our group before. Results indicate that the process integration of the AOS nTFT and poly-Si pTFT for monolithic IC is successful. The electrical characteristics of CMOS TFT inverter are pretty good. The voltage gain is ~ 25, the mid voltage is ~ 0.5 Vdd, and the high/low noise margins are large and approximately equal.In order to further improve the performance of nTFT, a novel tungsten (W) dopant was applied to replace gallium (Ga) for ASO film due to its lower price and higher oxygen bond dissociation energy. With higher oxygen bond dissociation energy, the oxygen vacancy can be well controlled and the device may achieve better electrical and reliability characteristics. It is found that the a-IWZO nTFT shows a ION/IOFF value of 7.8 order and a S.S. value of 109 mV/decade. Furthermore, the mobility of a- IWZO TFT is about 2 times higher than that of a-IGZO TFT. The a-IWZO TFT with tiny W dopant as the carrier suppressor can exhibit a smaller S.S. value, suggesting that the channel can be effectively controlled even with higher channel conductivity.To further improve the performance of pTFT, a polycrystalline germanium (poly-Ge) junctionless (JL) TFT is studied. The implantation and activation processes are not required for poly-Ge JL device because the vacancy and interstitial in poly-Ge film can act as acceptors, which naturally turn the film into p-type. However, Ge with poor thermal stability is very sensitive to process temperature. The Ge sub-oxides at Ge surface have lower bandgap, more oxide traps, and interface states, and they may diffuse into gate dielectric after thermal process, resulting in degradation of gate dielectric. The desorption and diffusion of GeOx can be suppressed by nitridation process on interfacial layer (IL) at high-k/Ge. Therefore, in this work, poly-Ge JL pTFT devices with various ILs including GeO2, GeON, O2 plasma-treated HfN, and O2 plasma-treated Al2O3 HfO2 are investigated and compared. The optimal IL for poly-Ge pTFT could be expected. Then, a CMOS device by integrating AOS nTFT and poly-Ge pTFT with a monolithic architecture will be performed as well.

Bias stability of solution-processed In2O3 thin film transistors

We report the effect of bias stress on the drain current and threshold voltage of n-channel thin-film transistors based on solution processed In2O3 layers. Application of a positive gate bias for variable time-periods led to displacements of the transfer curves in the positive gate bias direction. On switching off the gate bias, the transfer curves returned close to their pre-stress state on a timescale similar to that when the gate bias was switched on. The time dependence of the threshold voltage shift is described well by a stretched-exponential model. The temporal behaviour of the threshold voltage shifts is consistent with charge trapping as the dominant effect, although some defect formation cannot be ruled out.

Rapid Photonic Processing of High-Electron-Mobility PbS Colloidal Quantum Dot Transistors.

Recent advances in solution-processable semiconducting colloidal quantum dots (CQDs) have enabled their use in a range of (opto)electronic devices. In most of these studies, device fabrication relied almost exclusively on thermal annealing to remove organic residues and enhance inter-CQD electronic coupling. Despite its widespread use, however, thermal annealing is a lengthy process, while its effectiveness to eliminate organic residues remains limited. Here, we exploit the use of xenon flash lamp sintering to post-treat solution-deposited layers of lead sulfide (PbS) CQDs and their application in n-channel thin-film transistors (TFTs). The process is simple, fast, and highly scalable and allows for efficient removal of organic residues while preserving both quantum confinement and high channel current modulation. Bottom-gate, top-contact PbS CQD TFTs incorporating SiO2 as the gate dielectric exhibit a maximum electron mobility of 0.2 cm2 V–1 s–1, a value higher than that of control transistors (≈10–2 cm2 V–1 s–1) processed via thermal annealing for 30 min at 120 °C. Replacing SiO2 with a polymeric dielectric improves the transistor’s channel interface, leading to a significant increase in electron mobility to 3.7 cm2 V–1 s–1. The present work highlights the potential of flash lamp annealing as a promising method for the rapid manufacture of PbS CQD-based (opto)electronic devices and circuits.

Power Saving High Performance Deep-Ultraviolet Phototransistors Made of ZnGa2O4 Epilayers

Single-crystalline ZnGa2O4 epilayers with different diethylzinc (DEZn) flow rates were successfully grown on sapphire substrates. By decreasing the DEZn flow rate and keeping the deposition time constant, the operational mode of the transistors changed from depletion mode (D-mode) to enhancement mode (E-mode). The relevant electrical properties and physical characteristics are well presented and verified. An E-mode (DEZn = 10 sccm) n-channel thin-film transistor was fabricated for deep-ultraviolet (DUV) phototransistor application. In the phototransistor, the photocurrent gain values increased substantially in the DUV region, the peak value of which measures 1.54 × 102 at 240 nm. The superior performance of DUV phototransistors is correlated to the improvement in the quality of materials.

Wide band gap pyromellitic diimides for photo stable n-channel thin film transistors

Wide energy gaps of PyDI derivatives lead to excellent photostability in OFETs at illumination conditions and transparency on transparent substrates.