N-channel MOS Devices Research Articles

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

Carrier capture and emission properties of silicon interstitial defects in near SiC/SiO2 interface region

As the origin of near interface traps in silicon carbide (SiC)/SiO2 system, Si interstitial defects can affect the stability of SiC metal-oxide-semiconductor field-effect transistor (MOSFET) devices. Models are established based on the density functional theory to investigate the carrier capture and emission properties of Si interstitialdefects with two configurations in the near interface region on SiO2 side. Calculation results indicate the capture ability of Si–Si–Si configuration is strong for holes but weak for electrons, whereas that of Si–Si–O is strong for holes and electrons. Hence, these two configurations affect the stability of p-channel MOS and n-channel MOS devices in different degrees. For the charge emission ability, Si–Si–Si configuration has strong emission ability for electrons and holes, whereas Si–Si–O has a strong ability to emit electrons but weak ability to emit holes. The discrepancy of charge emission ability makes each configuration affect the stability of device in different ways, including charge exchange with channel and Coulomb scattering. This work helps understand the mechanisms of deterioration in reliability caused by SiC near-interface oxide defects.

A Novel High-Voltage Pseudo-p-LDMOS Device With Three Current Conductive Paths

A new concept high-voltage pseudo-p-channel lateral double-diffused MOS (p-LDMOS) with multiple current paths for conduction is proposed and investigated in this paper. The proposed power device consists of two hole current paths (p-channel MOS device) and one electron current path (n-channel MOS device). The gate of the n-channel device is automatically controlled by an induced signal inside the chip, thus the proposed device can be considered as a p-LDMOS with more than 66.2% reduction of specific on-resistance in comparison with the conventional p-LDMOS device. Furthermore, the proposed device has a much better safe operation area, since the compensation of the electric flux density brought by electron and hole currents.

CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications.

In this work, we present a CMOS-integrated low-noise junction field-effect transistor (JFET) developed in a standard 0.18 pm CMOS process. These JFETs reduce input-referred flicker noise power by more than a factor of 10 when compared to equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input, significant for many applications in bioelectronics.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: Application to high-k material HfO2 based MOS devices

In this paper presents a straightforward efficient investigation of tunneling current density for ultra thin oxide layer based metal-oxide-semiconductor (MOS) devices to realization the gate current as a function of applied potential and oxide thickness. Solutions to the Schrödinger's wave equation are evolved for the different potential energy regions of the MOS device considering appropriate effective mass for each region. For finding approximate mathematical solutions to linear differential equations using spatially changeable coefficients the Wentzel-Kramers-Brillouin (WKB) approximation technique is considered. A p-substrate based n-channel MOS device has been analyzed consisting of SiO2 material as the oxide dielectric along with high-k material HfO2. The tunnel resistivity is correspondingly assessed employing this tunneling current density model. Synopsys Technology Computer Aided Design (TCAD) tool results are employed to validate the analytical model. Tremendous agreements among the results are observed.

Total dose dependence of hot carrier injection effect in the n-channel metal oxide semiconductor devices

The equipment and devices which are long-time running in space are affected by space radiation effects and hot carrier injection effects at the same time which would reduce their optional times. Normally, the single mechanism test simulation method is used on the ground simulation test but the multi-mechanism effect affects the space equipments and devices, including total irradiation dose effect, hot carrier injection effect, etc. The total dose dependence of hot carrier injection (HCI) effect in the 0.35 m n-channel metal oxide. semiconductor (NMOS) device is studied in this paper. Three samples are tested under different conditions (sample 1# with total irradiation dose (TID) and HCI test, sample 2# with TID, annealing and HCI test, sample 3# only with HCI test). The results show that threshold voltage of NMOS device with 5000 s HCI test after 100 krad (Si) total dose radiation has been negatively shifted then positively during total dose irradiation test and HCI test, and the threshold is higher than that of the device without radiation test. But the threshold voltage shift of NMOS device with 5000 s HCI test and 200 h annealing test after TID test is higher than that of the devices without radiation test and lower than that of the devices without annealing test. That is, the parameters of NMOS device vary faster with the combined effects (including the total dose irradiation effect and HCI effect) than with single mechanism effect. It is indicated that the hot electrons are trapped by the oxide trap charges induced by irradiation effect and then become a recombination centre. And then the oxide trap charges induced by irradiation effect reduce and become negative electronic. The interface trap charges induced by irradiation effect are reduced and then increased it is because the electrons of hole-electron pairs in the Si-SiO2 interface are recombined by oxide traps in the oxide during the forepart of HCI test but then the electrons are trapped by interface traps in the Si-SiO2 interface because the electrons from source area are injected to interface during the HCI test. So the threshold voltage is positively shifted due to the negative oxide trap charges and interface trap charges. The association effect is attributed to the reduction of oxide traps induced by recombination with hot electrons and the increase of the interface traps induced by irradiation trapped hot electrons.

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-kDielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-<i>k</i>Dielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-k Dielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

It was found that the structural properties with gadolinium (Gd) and europium (Eu) incorporation into nickel (Ni) fully silicided (FUSI) gate electrodes are markedly different and resulted in different degrees of effective work function modulation. It was found that Ni–Gd alloys tend to form stable compounds during silicidation and produced a Si-rich layer with amorphous/nanocystalline structure near the FUSI gate electrode/high-k dielectric interface. This compositional and structural change is the main mechanism responsible for effective work function modulation with Gd incorporation. However, in the case of Europium, Eu atoms tend to segregate outside the Ni-FUSI layer during silicidation and resulted in a uniform NixSiy layer with Eu pile-up layer at the FUSI gate electrode/high-k dielectric interface. This pile-up is believed to be the main cause of effective work function modulation with Eu incorporation. It was also found that the incorporation of Gd and Eu metals into Ni-FUSI gate can remotely scavenge the interfacial oxide layer resulting in lower equivalent oxide thickness (EOT) of the device.

Completely Quantum–Mechanical Extraction of Equivalent Oxide Thickness of PMOS Gate Insulator

To cope with the growing problem of device variability from the viewpoint of global variability, the authors developed a completely quantum-mechanical (QM) capacitance voltage (C-V) simulator of polycrystalline-Si-gate p-channel metal-oxide-semiconductor (PMOS) devices in a similar way to the previous one for n-channel MOS (NMOS). The simulator was entirely based on experimental results and did not adopt any assumptions, which were inevitable in the other simulators, to implement the QM effects. Experimental C-V curves were almost completely reproduced by the simulator. The authors further extracted the equivalent oxide thicknesses (EOTs) of NMOS and PMOS devices, which were formed on the same dies, using this and the previous simulators. The EOTs of PMOS devices were always equal to or larger than those of the NMOS devices. The difference increased with a total dosage of fluorine atoms that were selectively introduced into the PMOS devices by BF2+ or F+ implantations during fabrication steps. It was almost zero in the case of small F dosages, as it should be. These results support the validity of this simulator. During the development of the simulator, the authors again confirmed that the relative dielectric constant of SiO2, grown at 950°C or lower, is larger than the conventional value of 3.9.

N-Channel MOSFETs Fabricated on SiGe Dots for Strain-Enhanced Mobility

The silicon germanium dots grown in the Stranski-Krastanow mode are used to induce biaxial tensile strain in a silicon capping layer. A high Ge content and correspondingly high Si strain levels are reached due to the 3-D growth of the dots. The n-channel MOS devices, referred to in this letter as DotFETs, are processed with the main gate segment above the strained Si layer on a single dot. To prevent the intermixing of the Si/SiGe/Si structure, a novel low-temperature FET structure processed below 400°C has been implemented: The ultrashallow source/drain junctions formed by excimer-laser annealing in the full-melt mode of ion-implanted dopants are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing, and compared to reference devices, an average increase in the drain current of up to 22.5% is obtained.

A Combined Study of p- and n-Channel MOS Devices to Investigate the Energetic Distribution of Oxide Traps After NBTI

The aim of this paper is to highlight the effect of gate bias switches and charge pumping (CP) on oxide trap and interface-state recovery. In general, variations in gate bias correspond to shifts of the Fermi level (E F) across the silicon band gap and trigger carrier exchange between stress-induced oxide traps and the silicon substrate. Our measurements strongly indicate that interface-state recovery is accelerated by the CP measurement itself, whereas oxide-trap occupation can be controlled more efficiently by slow Fermi level switches. Oxide-trap neutralization/charging by electron/hole capture works similarly to interface states but with larger time constants indicating inelastic carrier tunneling between the silicon substrate and stress-induced donorlike oxide traps. In a combined study, we compare threshold-voltage shifts and recovery of identically processed NMOS and PMOS devices which allows us to gain access to the full silicon band gap by appropriate gate biasing. Additional CP measurements on identically stressed reference devices allow us furthermore to differentiate quantitatively between interface-state and oxide-trap contributions. Finally, by referring oxide-trap-dependent V TH shifts after stress to certain gate voltages during recovery, energetic profiling of oxide traps with respect to the Fermi level position becomes possible.

Temperature dependent time-to-breakdown ( TBD) of TiN/HfO 2 n-channel MOS devices in inversion

Effect of temperature on time-to-breakdown ( T BD) of n +-ringed n-channel MOS capacitors with atomic layer deposited TiN/HfO 2 based gate stacks is studied. While interfacial layer (IL) growth condition and thickness varied the high- κ layer thickness and processing was unchanged. These devices were investigated by applying a constant voltage stress (CVS) in inversion (substrate injection) at room and elevated temperatures. For high electric fields (10–15 MV/cm) across IL, it is observed that T BD is thermally activated irrespective of IL condition. Activation energies (2–3 eV after correction), found from Arrhenius plots of T BD for different IL conditions, show good matches with those associated with field-driven thermochemical model of breakdown developed for SiO 2.

High Channel Mobility in P-Channel MOSFETs Fabricated on 4H-SiC (0001) and Non-Basal Faces

P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.

Negative bias temperature instability in n-channel power VDMOSFETs

Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal V T shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall V T instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model.

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.

Electron-Scattering Mechanisms in Heavily Doped Silicon Carbide MOSFET Inversion Layers

Hall-effect measurements of n-channel MOS devices were used to determine the main scattering mechanisms limiting mobility in SiC MOSFETs. MOS-gated Hall characterization, which was performed as a function of gate bias and body bias, indicates that surface-roughness scattering and Coulomb scattering are the main scattering mechanisms limiting electron mobility in SiC MOSFETs at room temperature. A charge-sheet model, including incomplete ionization and Fermi-Dirac statistics, is used to calculate the surface electric fields in order to develop an expression for surface-roughness scattering. In the samples used for this paper, at electron sheet densities less than 1.8times1012 cm-2, Coulomb scattering dominates, while surface roughness is dominant at higher sheet densities.

Breakdown characteristics of nFETs in inversion with metal/HfO 2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO 2 high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (⩽3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown ( T BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG=50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31 Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff=100 nA/mum) was obtained for Ni 31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

Reduction of Polysilicon Gate Depletion Effect in NMOS Devices Using Laser Thermal Processing

One critical issue in advanced semiconductor processing is to have adequate dopant activation in the polycrystalline silicon (poly-Si) gate to minimize carrier depletion at the gate/gate oxide interface (poly-depletion). We demonstrate a novel technique, using laser thermal processing, to form super-doped n + -poly-Si gates on ultrathin gate oxides. The results indicate that the poly-depletion effect in n-channel metal-oxide-semiconductor (NMOS) devices can be significantly reduced if the entire as-deposited amorphous silicon gate melts upon laser irradiation. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after laser processing at a high fluence.