N-channel MOS Devices Research Articles

Effects of Methyl Silsesquioxane Electron-Beam Curing on Device Characteristics of Logic and Four-Transistor Static Random-Access Memory

The as-spun methyl silsesquioxane (MSQ) film cured by an electron beam (e-beam) did not show water absorption after a five-day exposure to ambient air. MSQ was applied to the triple-level metal (TLM) Logic and double-level metal (DLM) four-transistor (4-T) static random-access memory (SRAM) as intermetal dielectric by means of the non-etchback process. When MSQ treatment conditions were properly controlled, the top layer of the as-spun films was cured by e-beam exposure while the bottom layer of the film was thermally cured for a short period of time. The as-cured MSQ offered good surface planarity. In addition, neither via poisoning, bowing nor cracking was observed. The results showed that, by the application of the e-beam cured MSQ in the fabrication of interconnect structures, the cache time of DLM 4-T SRAM could be improved to 10 ns compared with 11.5 ns for the SRAM fabricated using the conventional furnace cure spin-on-glass (SOG) process (400°C annealing for one hour). E-beam exposure has little effect on n-channel metal-oxide-semiconductor (NMOS) device characteristics, such as saturation current, threshold voltage and channel length. In contrast, e-beam exposure has a significant effect on p-channel MOS (PMOS) device characteristics, resulting in a shift of the threshold voltage as well as an increase in the channel length. It is notable that the e-beam exposure almost did not affect NMOS device characteristics in the 4-T SRAM, since the polysilicon load resistor could serve as a shield against electron bombardment. In such a case, the resistance of the polysilicon load resistor was significantly decreased.

A Model for Reverse Short Channel Effect and Capacitance‐Voltage Characteristics

A new model for simulating the reverse short channel effect and capacitance‐voltage (C‐V) characteristics of metal‐oxide‐semiconductor (MOS) transistors has been developed. Due to ion‐implantation and stress effects, the interface between Si and in the model described here has been assumed to be a nonuniform sink of interstitials. The simulator ALAMODE and the two‐dimensional (2D) process simulator TSUPREM4 were used to simulate doping profiles of n‐channel MOS (NMOS) devices. Using simulated 2D doping profiles, the threshold voltage and C‐V curves of NMOS devices were calculated. We show comparisons of the threshold voltage, C‐V curves, and channel doping profiles for extracted profiles using inverse modeling techniques and those simulated by ALAMODE and TSUPREM4. Using default model parameters in TSUPREM4, the doping profiles did not match extracted doping profiles well, but with the model described here incorporated into TSUPREM4 using calibrated model parameters, a good match between measurements and simulations was observed. The body effect and C‐V characteristics of NMOS devices are quantitatively predicted using parameters obtained from matching of experimental threshold voltage data. We describe the model and implementation and discuss the physical significance of the new model. © 1999 The Electrochemical Society. All rights reserved.

Gate technology for 0.1-μm Si complementary metal–oxide–semiconductor using g-line exposure and deep ultraviolet hardening

A gate technology for producing 0.1-μm gate length silicon complementary metal–oxide– semiconductor (CMOS) circuits has been developed by integrating g-line exposure, resist narrowing, deep UV hardening, and dry etching of nitride and polysilicon. The 0.1-μm gate length n-channel and p-channel MOS devices have been previously processed via e-beam lithography using a chemically amplified e-beam resist. However, the e-beam technique suffers from low throughput, especially in processing complex circuits. In addition, the chemically amplified e-beam resist requires prompt processing. Thus g-line exposure and photoresist narrowing was chosen as an alternative. The resist features were narrowed from 0.5 μm down to 0.1 μm using low power O2 plasma. The profile of the narrowed resist shows that the body is thicker than the base. The narrowed resist features were then hardened by deep UV in order for the photoresist to withstand the subsequent nitride etch using CHF3 reactive ion etching (RIE). The obtained nitride profile shows a rounded top which is expected from the profile of resist features. The subsequent polysilicon etch was done using a two-step Cl2 RIE. The obtained profile of polysilicon is comparable to that previously obtained using e-beam lithography. This gate technology was used to successfully fabricate 0.1-μm circuits such as conventional unloaded CMOS ring oscillators and 2:1 frequency dividers.

Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation

Presents a physical model of reverse short-channel effects on threshold voltage caused by lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by ion implantation in source/drain region of n-channel MOS devices. Based on the process and device simulation, it is shown that lateral diffusion of the Frenkel pairs enhances diffusion of channel dopant, and results in nonuniform lateral distribution. This phenomenon causes the threshold voltage increase in the short-channel devices. The authors extracted parameters on point-defect diffusion from the comparison of calculated results with experimental data on threshold voltage. Calculated arsenic profile in the source/drain region using those parameters shows good agreement with the experimental data measured by secondary ion mass spectroscopy (SIMS). The close agreement between simulation and experimental results both on the arsenic profile in source/drain region and threshold voltage confirms the validity of the model and extracted parameters. >

Low-temperature CV dispersion in MOS devices

A study is reported of the dispersion seen in the accumulation and depletion regions, of the C-V curve in n-channel MOS devices in the temperature range 30-45 K. It is concluded that the dispersion observed in these experiments is caused by time-constant effects, due to the substrate resistance and not caused by dopant atom emission time constant effects. From the measured admittance as a function of temperature and frequency, the acceptor energy level is determined to within +or-0.4 meV. >

Predicting switched-bias response from steady-state irradiations MOS transistors

A novel semiempirical model of radiation-induced charge neutralization is presented. This model is combined with 12 heuristic guidelines derived from studies of oxide- and interface-trap charge ( Delta V/sub ot/ and Delta V/sub it/) buildup and annealing to develop a method to predict MOS switched-bias response from steady-state irradiations, with no free parameters. For n-channel MOS devices, predictions of Delta V/sub ot/, Delta V/sub it/, and mobility degradation differ from experimental values through irradiation by less than 30% in all cases considered. This is demonstrated for gate oxides with widely varying Delta V/sub ot/ and Delta V/sub it/ and for parasitic field oxides. Preliminary results suggest that n-channel MOS Delta V/sub ot/ annealing and Delta V/sub it/ buildup following switched-bias irradiation and through switched-bias annealing also may be predicted with less than 30% error. The p-channel MOS response at high frequencies (>1 kHz) is more difficult to predict. >

Back Channel Degradation and Device Material Improvement by Ge Implantation

AbstractBecause of potential “back channel” leakage problems in silicon-oninsulator (SOI) metal-oxide-semiconductor (MOS) devices, especially n-channel MOS devices which must operate in an ionizing radiation environment, it is desirable to produce Separation by IMplantation of OXygen (SIMOX) wafers which have a layer of poor quality silicon near the Si/buried SiO2 interface. At the same time, these wafers must have low defect, high quality silicon near the wafer surface for device fabrication.We have demonstrated that with Ge ion implantation and solid phase epitaxy regrowth, the surface region of the silicon top layer of the SIMOX wafer is improved and the region adjacent to the buried SiO2 is degraded. These results have been observed by RBS/channeling, XTEM, and plane view TEM.

A new analytical model of the "Bird's beak"

The numerical simulation of technological processes is very important for the fabrication of integrated circuits. The authors have developed the two-dimensional simulator OSIRIS allowing the simulation of ion implantation and redistribution of dopants in silicon. An original analytical model for oxide growth has been developed that gives very good simulation of the "bird's beak" of SEMIROX structures. As an example, a complete simulation of an n-channel MOS device is presented with the redistribution impurity profiles and the oxide layer shape at the end of the process.

Realization of quaternary logic circuits by n-channel MOS devices

A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.

Monolithic integration of GaAs/AlGaAs modulation-doped field-effect transistors and N-metal-oxide-semiconductor silicon circuits

We have demonstrated for the first time the compatibility of GaAs with Si N-channel metal-oxide-semiconductor (NMOS) transistors by successfully fabricating GaAs/AlGaAs modulation-doped field-effect transistors (MODFET’s) on a Si wafer containing NMOS devices. The MODFET’s with 2 μ gate length on 6 μ channels exhibited transconductances of 120 and 180 mS/mm at 300 and 77 K, respectively. The NMOS devices exhibited little if any performance degradation in going through the GaAs growth and fabrication process. These results show that the monolithic integration of GaAs devices with Si devices is possible, which may add a new dimension to the already exploding world of electronics.

The Effect of Operating Frequency in the Radiation Induced Buildup of Trapped Holes and Interface States in MOS Devices

Both n-channel and p-channel MOS transistors, fabricated with a radiation hardened 3-4 um process, were irradiated at various operating frequencies and biases. The n-channel devices showed a larger rebound effect when alternately biased 'off' and 'on' during irradiation than for the cases of being biased either 'off' or 'on' during the irradiation. The p-channel devices showed a smaller threshold voltage shift when alternately biased 'off' and 'on' during irradiation compared to devices which were biased either 'off' or 'on' during the irradiation. The contributions of trapped holes and interface states on the observed threshold voltage shifts were determined through subthreshold current measurements. This research showed the source of this alternating bias effect on the radiation response of MOS devices to be reduced hole trapping and increased interface state buildup in n-channel MOS devices. In p-channel devices, reduced hole trapping is the primary source of this effect.

Liqiuid Crystal Display Fabricated from Laser Recrystallized Silicon on Bulk Fused Silica

ABSTRACTThis paper discusses four aspects of fabrication of an active address liquid crystal array from laser recrystallized polycrystalline silicon: recrystallization, processing, device performance and array fabrication. The recrystallization process produces material which is imperfect by silicon wafer standards, but which contains few incoherent defects. The material was used to fabricate discrete n-channel MOS devices which had consistent off currents of 10−11 amps (0.4pA/μm of channel width) and on currents of 10−4 amps. Device threshold is controlled to + 200 mV and channel mobility is 500 to 600 cm2 /V-sec. The crossovers between Al/1% Si source and degenerately doped polycrystalline silicon gate lines were fabricated by use of high temperature reflowed, phosphorus doped chemical vapor deposited SiO2. Completed arrays had very few defects (no crossover defects and 0.3% bad devices).

A re-examination of practical performance limits of scaled n-channel and ϱ-channel MOS devices for VLSI

The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2 μm gate length including all of the major effects such as source/drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different power supply scenarios. From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined. Based on these calculations, some modifications to straight-forward scaling are considered.

Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's

Drain avalanche hot-carrier (DAHC) injection, which imposes the most severe limitations on n-channel MOS device design, is investigated from the viewpoint of surface-state generation and its localized area in the channel. It is shown, using the charge pumping technique, that the surface states are mainly created by hot-hole injection, and its small degraded area stretches toward the source region with increased stress time. A remarkable correlation between the increase of surface-state density, transconductance degradation, and substrate current is also described. In addition, to clarify the role of hot-hole injection, p-channel devices, as well as n-channel devices, are used, and hot-hole injection is shown to create more surface states than hot-electron injection.

Electron-beam direct writing of n-MOS devices and analysis of overlay and linewidth accuracies

Electron-beam direct writing of experimental, n-channel MOS devices is reported. This work has been done to identify the relative potential advantages and disadvantages of e-beam direct writing as one of the candidates for submicrometer lithography technology. The e-beam machine used in this work is a vector-scan system with a laser interferometry positioned stage. Both wafer registration and chip-by-chip registration schemes have been implemented in a simple, unified algorithm. Signal-to-noise ratio and process compatibility have been considered in determing the structure of alignment marks, with shallow (∠1.0 μm) grooves in the silicon wafer being adopted. Analysis of error factors, both instrumental and process related, which influence registration accuracy and linewidth control, has been carried out using a series of special experiments. It has been found that errors are rather evenly distributed over various causes. Electron beam direct writing has been found to provide excellent linewidth control and overlay accuracy, with 3 sigma limits of 0.1 and 0.5 μm, respectively.

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.

Damage Introduced by Second Breakdown in N-Channel MOS Devices

Failures in an N-channel MOS device as a result of electrical overstress are discussed in terms of “second breakdown transition”.1,2) In the second breakdown state, large power, as much as 500–5,000 mW, is dissipated in the drain depletion layer. The power dissipation leads either to aluminum migration from the gate electrode to the substrate through the gate oxide or to the degradation of transistor properties. Most of the aluminum migration occurs in a localized area of the substrate surface, where the depletion layer of the drain region extends widely. The second breakdown transition in an N-channel MOS device is attributable to minority carrier injection from the source region to the substrate and to an increase in the impact ionization current in the drain depletion layer. The critical drain voltage of the second breakdown transition depends on the source-substrate bias, the substrate resistivity, the channel length and the gate voltage.