Gate technology for 0.1-μm Si complementary metal–oxide–semiconductor using g-line exposure and deep ultraviolet hardening

Abstract

A gate technology for producing 0.1-μm gate length silicon complementary metal–oxide– semiconductor (CMOS) circuits has been developed by integrating g-line exposure, resist narrowing, deep UV hardening, and dry etching of nitride and polysilicon. The 0.1-μm gate length n-channel and p-channel MOS devices have been previously processed via e-beam lithography using a chemically amplified e-beam resist. However, the e-beam technique suffers from low throughput, especially in processing complex circuits. In addition, the chemically amplified e-beam resist requires prompt processing. Thus g-line exposure and photoresist narrowing was chosen as an alternative. The resist features were narrowed from 0.5 μm down to 0.1 μm using low power O2 plasma. The profile of the narrowed resist shows that the body is thicker than the base. The narrowed resist features were then hardened by deep UV in order for the photoresist to withstand the subsequent nitride etch using CHF3 reactive ion etching (RIE). The obtained nitride profile shows a rounded top which is expected from the profile of resist features. The subsequent polysilicon etch was done using a two-step Cl2 RIE. The obtained profile of polysilicon is comparable to that previously obtained using e-beam lithography. This gate technology was used to successfully fabricate 0.1-μm circuits such as conventional unloaded CMOS ring oscillators and 2:1 frequency dividers.