Gate technology for 89 GHz vertical doping engineered Si metal–oxide semiconductor field effect transistor

Abstract

The gate definition performed on a vertical doping engineered metal–oxide semiconductor field effect transistor is described. The fabricated gates were as narrow as 0.15 μm. For writing narrow gates, e-beam lithography and a chemically amplified negative resist SAL603 were used. The alignment between the gate level and underlying Nikon-printed levels was made using 0.8 μm deep trenched marks. The gate patterning was done with reactive ion etching (RIE) in CHF3 gas to etch a nitride layer which serves as a gate etch mask and subsequently in a Cl2 gas used to etch the polysilicon gate. A sidewall spacer was formed with a two step etch using CF4 RIE and CHF3 RIE after deposition of a 2000 Å TEOS film. After metallization the n-channel devices have measured excellent device characteristics.