N-channel MOS Transistors Research Articles

Electrical characterization of n-channel MOSFETs with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition

This study reports on n-channel MOS transistors using very thin oxynitride gate dielectrics deposited by Low-Pressure Rapid Thermal Chemiical Vapor Deposition (LPRTCVD). The threshold voltage, the transconductance, the fast and slow trap densities, the low field mobility and its reduction factors have been investigated as a function of the nitrogen concentration in the film. The threshold voltage was found to decrease linearly with the nitrogen concentration, primarily because of the increase of the positive insulator charge density. At the same time, it has been shown that the quadratic mobility reduction factor is lower for a LPRTCVD oxynitride (and nearly constant with the nitrogen concentration) in comparison to a thermal oxide. From this high field mobility attenuation, a lower transconductance is then expected for oxynitride-based transistors. Finally, we have shown that the presence of nitrogen in the oxide seems to induce more donor than acceptor traps at the oxynitride-silicon interface.

Comprehensive Analysis of an Isolation Area Obtained by Local Oxidation of Silicon Without Field Implant

Isolation area, obtained by local oxidation of silicon (LOCOS) without field implant, naturally shows a high sensitivity of the leakage current to fixed charges in metal oxide semiconductor (MOS) parasitic transistors. It has been shown that during the deposition of the nitride capacitor insulator-layer, fixed charges are generated in the underlying plasma-deposited oxides. The behavior of the P-channel MOS (PMOS) parasitic transistor can be well accounted for by considering fixed charge creation in the thick part of the gate insulator. In the case of the N-channel MOS (NMOS) transistor, the leakage current is controlled by the bird's beak region where a high interface state density exists. The NMOS behavior has been explained taking into account the charge creation as well as a decrease in interface state density during nitride deposition. A new “recipe” for the nitride deposition based on a very low thermal budget has been established. Finally, a high threshold voltage and a reasonably low leakage current have been achieved for both the NMOS and PMOS parasitic transistors.

Strained Si n-channel metal–oxide–semiconductor transistor on relaxed Si1−xGex formed by ion implantation of Ge

Ge implantation followed by high-temperature solid phase epitaxy was used to form a relaxed substrate, eliminating need for the growth of relaxed Si1−xGex layers. Upon this film, a 2000 Å buffer layer of Si0.85Ge0.15 followed by a 200 Å strained Si layer was grown by ultrahigh-vacuum chemical vapor deposition. For comparison, unstrained Si epitaxial films and a 2000 Å thick film of Si0.85Ge0.15 (on unimplanted Si) followed by 200 Å of Si were used. n-channel metal–oxide–semiconductor transistors were fabricated and their dc characteristics were examined. Strained Si devices show a 17.5% higher peak linear μFE than control devices as a result of higher electron mobility in the strained Si channel. This work demonstrates a simple method for the formation of strained Si layers.

Numerical simulation of creation-passivation kinetics of interface traps in irradiated n-channel power VDMOSFETs during thermal annealing with various gate biases

Influence of gate bias on creation-passivation processes of interface traps in irradiated n-channel MOS transistors during thermal annealing has been investigated. The experimental results, which show the dependence of these processes on gate bias, are explained by combined hydrogen-water (H-W) model. The modelling of kinetics of creation and passivation of interface traps, based on bimolecular theory and numerical analysis, is also performed. Numerical simulation shows that H-W model predicts the maximum of interface trap density and latent interface trap buildup during thermal annealing.

Positive oxide charge from hot hole injection during channel-hot-electron stress

Positive oxide charge build up (+Q/sub OT/) during channel-hot-electron (CHE) stress in silicon n-channel MOS transistors from 1.0 and 0.35-/spl mu/m technologies is monitored by the direct-current current-voltage (DCIV) method. Experiments demonstrated the following: (1) +Q/sub OT/ is located over the drain/channel junction space-charge-region, (2) threshold hole kinetic energy equals the SiO/sub 2//Si hole barrier, /spl phi//sub Xh/=4.25 eV, (3) the oxide-charging carriers near the threshold are the secondary hot holes generated by interband impact-collision and Auger-recombination of the CHEs with thermalized holes impact-generated in the n/sup +/ drain by CHEs, and (4) the smallest threshold drain acceleration voltage from interband Auger-recombination among the four intrinsic pathways is smaller than /spl phi//sub Xh/ by E/sub Gap/-Sl, 4.25 V-1.12 V=3.13 V.

Interfacial hardness enhancement in deuterium annealed 0.25 μm channel metal oxide semiconductor transistors

Interfacial degradation induced by hot-electron injection has been studied in n-channel metal oxide semiconductor transistors with channel lengths down to 0.2 μm. The devices were annealed in either H2 or D2 containing atmospheres. The channel transconductance and threshold voltage variations induced by hot-electron injection into the gate are consistent with interface state generation. Charge pumping experiments confirm this conclusion. The lifetime for a 10% reduction in the transconductance is enhanced by ∼10 times for devices annealed in D2 containing atmospheres as compared to those annealed in H2.

Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

Design trade-off relations for the last stage of a complementary metal-oxide-semiconductor (CMOS) off-chip driver that meets a prespecified normalized maximum simultaneous switching ground noise and a prespecified normalized time when the switched N-channel metal-oxide-semiconductor transistor (NMOST) leaves the saturation region are provided in this paper. To maintain system performance with control of 90-10% fall time and/or 10-90% rise time, the proposed trade-off relations are then modified numerically for design with prespecified fall/rise time. The proposed trade-offs relate the normalized simultaneous switching noise and the normalized switching time to driver size, load capacitance, ground/power path inductance, number of switching drivers, and input signal rise time. It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance. Such a feature will be demonstrated by SPICE simulations of circuits based upon the proposed design relations and MOS1 model, which agrees well with the design goals.

Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling

We have extensively measured and analyzed the current mismatch of a small-size n-channel MOS transistor of 2 /spl mu/m/spl times/2 /spl mu/m operated in weak inversion with its p-well-to-n/sup +/-source junction forward and reverse biased. The case of slightly forward biasing the well-to-source junction represents the action of a gated lateral bipolar transistor in low level injection. The measured dependencies of the mismatch in weak inversion on the back-gate forward and reverse biases have been successfully reproduced by a new simple statistical model. From the experimental data, we suggest that i) subthreshold circuits should be carefully designed for suppression of mismatch arising from back-gate reverse bias, and ii) a gated lateral bipolar action in low level injection may be utilized as a new method of improving the transistor matching.

A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs

Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quantum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in today's widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that predicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. (1994) has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors.

Neural network implementation using a single MOST per synapse

A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well.

Identification of plasma induced failure modes in the development of a bipolar‐complementary metal–oxide–semiconductor process

Development of a bipolar‐complementary metal–oxide–semiconductor process encountered metal–oxide–semiconductor (MOS) device failure behaviors that were traced to a single processing plasma source. Despite the fact that the process employed relatively thick 500 Å MOS gate oxides and was made in a manufacturing line that also produces a complementary metal–oxide–semiconductor product with gates below 200 Å, significant plasma damage effects were identified. Four distinct failure signatures were observed: shorted n‐channel metal–oxide–semiconductor transistor (NMOS) gates, leaky NMOS gates with functioning channels, parasitic depletion mode conduction at the ends of the enhancement NMOS device channel, and p‐channel metal–oxide–semiconductor transistor (PMOS) threshold shift as observed in a differential amplifier input offset. Test devices were specifically designed to monitor plasma damage through various gate antenna configurations. Device protection fuses were also employed to identify the cause of the failures as electrical damage induced during the backend of wafer processing. Although the methodology was successful, the experience points toward significant improvements that can be made and will be employed in future development and characterization efforts on a routine basis. Sequential characterization of device performance from the first metal out quickly identified the plasma enhanced chemical vapor deposition tool used for final passivation deposition as the primary contributor to the plasma damage. Subsequent process flow changes did eliminate this source of plasma damage.

N-Channel Mos Transistors below 0.5 μm with Ultra-Shallow Channels formed by Low Temperature Selective Silicon Epitaxy

AbstractIn this paper, we present an application of ultra high Vacuum Rapid Thermal Chemical Vapor Deposition (UHV-RTCVD) to MOSFET channel engineering. MOSFETs were fabricated on ultra-thin (200 Å), moderately doped (l×1017 - 6×1018 cm−3) p-type epitaxial layers selectively grown in active areas defined by standard LOCOS isolation. The selective epitaxy was achieved using a novel Si2H6Cl2/B2H6 process at 800°C and at a total pressure under 30 mtorr. Low thermal budget processing techniques were emphasized to minimize spread in the channel doping profile. Threshold voltages below 0.6 V were obtained. Transistors with effective channel lengths of 0.45 μm exhibit subthreshold slopes from 78 to 92 mV/decade determined by the epitaxial channel doping density. We have found that by using ultra-thin channels, expected transconductance degradation at high channel doping densities can be minimized. Furthermore, ultra-thin channels help reduce the sensitivity of the threshold voltage on substrate bias. The results show that low temperature selective silicon epitaxy can be used to form ultra-shallow channel doping profiles that can enhance the performance of MOSFETs in the deep submicron regime.

An MOS four-quadrant analog multiplier based on the multitail technique using a quadritail cell as a multiplier core

An MOS four-quadrant analog multiplier using a quadritail cell as a multiplier core is presented. A quadritail cell operates as a multiplier core by adding proper combinations of the two input voltages to the individual gates of the four transistors in the core, and also, there are numerous combinations of the two input voltages for a quadritail cell to properly multiply the two input voltages. But all MOS multipliers using a quadritail cell with the proper added combinations of the two input voltages usually possess transfer characteristics equivalent to those of the multiplier proposed by Bult and Wallinga (1986) and by Bult (rediscovered by Wang (1991)). An input system for the MOS multiplier core can, of course, be realized by active devices and also by resistive dividers, if all the added inputs are positive-combinations. The proposed multiplication circuitry is widely useful since it Is operable on low voltage and can be simply implemented with n-channel MOS transistors and resistors in MOS technology. >

Sequential substrate and channel hot electron injection to separate oxide and interface traps in n-MOSTs

In the present work oxide traps present in the gate oxide of n-channel MOS transistors ( n-MOSTs) are filled by substrate hot electron (SHE) injection prior to channel hot electron (CHE) injection stress. By employment of SHE to fill existing oxide traps at low fields without generating interface traps, the contributions of oxide trap charging and interface trap generation on CHE induced n-MOST degradation may be separated. Using this sequential two-stage SHE/CHE stress, it is shown that (1) oxide trap charging and interface trap generation contribute to the threshold voltage shift and subthreshold distortion during short stress duration and (2) after the existing oxide traps are filled, interface trap generation dominates during long stress duration.

Monolithic integration of a silicon driver circuit onto a lead lanthanum zirconate titanate substrate for smart spatial light modulator fabrication

The monolithic integration of N-channel metal-oxide-semiconductor (NMOS) driver circuits in silicon thin films onto a lead lanthanum zirconate titanate (PLZT) substrate is reported. Two integration methods are compared. Both methods result in NMOS transistors that exhibit electrical properties that are close to those of transistors fabricated in bulk silicon. The characteristics of PLZT modulators driven by thin-film transistors are also similar to those of bulk PLZT modulators. These techniques promise new spatial light modulators of high complexity and performance that good-quality silicon and bulk PLZT can offer.

On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D/sub it/-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior. >

Evaluation and control of device damage in high density plasma etching

The effects of polysilicon etch plasma conditions on metal–oxide–semiconductor (MOS) capacitor breakdown and n-channel MOS transistor (NMOS) performance have been investigated. A high density electron cyclotron resonance (ECR) plasma source with multipolar magnetic confinement was integrated into a full NMOS process flow. The polysilicon etch plasma process parameters for designed experiments were microwave power, overetch time, rf bias, and plasma radial uniformity. MOS capacitor leakage currents increase with longer polysilicon edge lengths on gate oxide, higher ion density, and higher ion energy during the polysilicon overetch step. Lower NMOS transistor transconductance and higher threshold voltages correlate with longer overetch times and high microwave power and rf bias during the overetch step. Device performance degradation increases with decreasing channel length, and the exposure of the source and drain oxide edges to a high density flux is thought to be the main cause for observed degradation. A high rate, selective, and low damage polysilicon etch process can be obtained using a high density (≳1011 cm−3) and moderate ion energy (<30 eV) ECR discharge, with moderate power and zero applied rf bias during the overetch step.

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO/sub 2/ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Investigation of hot-carrier induced degradation in 0.1μm channel length n-MOSFET's

Ultra-short n-channel MOS transistors with gate lengths of 0.1μm have been analyzed in terms of hot-carrier induced degradation. The aging, performed at maximum substrate current, was monitored using the transconductance, drain current and charge pumping current. The results suggest that the degradation tends to be uniform, the degraded zone representing a large portion of the channel. Device lifetimes in excess of 10 years are predicted for nominal conditions of operation.

Correction factor in the split C– V method for mobility measurements

We present experimental and theoretical results concerning the accuracy of the split C– V method. The correction factor is introduced and computed as a function of terminal voltages, temperature, doping concentration and oxide thickness. Theoretical computations are compared with experimental data for two groups of n-channel and p-channel MOS transistors fabricated using dual-type poly-gate CMOS process.