mW Power Consumption Research Articles

A double-differential-input/differential-output fully complementary and self-biased asynchronous CMOS comparator

A novel fully complementary and fully differential asynchronous CMOS comparator architecture, that consists of a two-stage preamplifier cascaded with a latch, achieves a sub-100 ps propagation delay for a 50mVpp and higher input signal amplitudes under 1.1V supply and 2.1mWpower consumption. The proposed voltage comparator topology features two differential pairs of inputs (four in total) thus increasing signal-to-noise ratio (SNR) and noise immunity through rejection of the coupled noise components, reduced evenorder harmonic distortion, and doubled output voltage swing. In addition to that, the comparator is truly self-biased via negative feedback loop thereby eliminating the need for a voltage reference and suppressing the influence of process, supply voltage and ambient temperature variations. The described analog comparator prototype occupies 0.001mm2 in a purely digital 40 nm LP (low power) CMOS process technology. All the above mentioned merits make it highly attractive for use as a building block in implementation of the leadingedge system-on-chip (SoC) data transceivers and data converters.

Micro-pellistor with Integrated Porous Alumina Catalyst Support

Micro-pellistors capable to detect hydrocarbons below 50 mW power consumption at 550 oC operation temperature were developed by a novel processing technique. On the top of the full membrane type micro-heaters 1.4μm thick porous alumina was formed by laterally selective electrochemical etching of the deposited aluminum layer. The porous alumina of the active element is selectively covered by finely dispersed Pt catalyst using alternative methods; such as dropping of H2[PtCl6] and sputtering technique, all aiming at deposition of controlled volume and structure of the catalyst. Constant current method in a Wheatstone-bridge configuration was applied in functional tests.

Monitoring Power Data: A first step towards a unified energy efficiency evaluation toolset for HPC data centers

The energy consumption of High Performance Computing (HPC) systems, which are the key technology for many modern computation-intensive applications, is rapidly increasing in parallel with their performance improvements. This increase leads HPC data centers to focus on three major challenges: the reduction of overall environmental impacts, which is driven by policy makers; the reduction of operating costs, which are increasing due to rising system density and electrical energy costs; and the 20 MW power consumption boundary for Exascale computing systems, which represent the next thousandfold increase in computing capability beyond the currently existing petascale systems. Energy efficiency improvements will play a major part in addressing these challenges.This paper presents a toolset, called Power Data Aggregation Monitor (PowerDAM), which collects and evaluates data from all aspects of the HPC data center (e.g. environmental information, site infrastructure, information technology systems, resource management systems, and applications). The aim of PowerDAM is not to improve the HPC data center's energy efficiency, but is to collect energy relevant data for analysis without which energy efficiency improvements would be non-trivial and incomplete. Thus, PowerDAM represents a first step towards a truly unified energy efficiency evaluation toolset needed for improving the overall energy efficiency of HPC data centers.

High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver

A multi-Giga-bit/s (up to 6 Gbps) and energy-efficient (1 pJ/bit/m) data link is formed by using hollow plastic cable and CMOS transceivers for short distance (8 m) digital communications. The demonstrated link couples/de-couples 60 GHz carried digital signals with roughly 6 dB loss per coupling into/from a hollow plastic cable made of relatively low-loss (~1.5 dB/m) Teflon, which is widely used for various home appliances. The CMOS transceivers are designed and implemented in 65 nm Foundry CMOS to support the intended 60 GHz operation with 28 mW power consumption under a 1 V supply.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

An Asymmetrical QPSK/OOK Transceiver SoC and 15:1 JPEG Encoder IC for Multifunction Wireless Capsule Endoscopy

This paper presents a chipset including an asymmetrical QPSK/OOK transceiver SoC and a JPEG image encoder for wireless capsule endoscopy. The transceiver SoC supports bi-directional telemetry for high data-rate image transmission with QPSK modulation and low data-rate command link with OOK modulation. A low power JPEG encoder is designed to compress raw image data with compression ratio as high as 15:1 using sub-sampling technique in YUV color plane. Implemented in 0.18 μm CMOS, the QPSK TX consumes 5 mW at -6 dBm of output power with 3 Mb/s data rate while the OOK RX achieves -65 dBm of sensitivity at 500 kb/s data rate with 4.5 mW power consumption. A prototype capsule has been implemented with the chipset and the performance has been verified with in vivo animal experiment. With duty cycling, the average power consumption of TX is 2.5 mW when transmitting at 3 fps frame rate.

An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

This paper presents a pipelined analog to digital converter (ADC) with reconfigurable resolution and sampling rate for biomedical applications. Significant power saving is achieved by turning off the sample-and-hold stage and the first two pipeline stages of the ADC instead of turning off the last two stages. The reconfiguration scheme allows having three modes of operation with variable resolutions and sampling rates. Reconfigurable operational transconductance amplifiers and an interference elimination technique have been employed to optimize power-speed-accuracy performance in biomedical instrumentation. The proposed ADC exhibits a 56.9 dB SNDR with 35.4 mW power consumption in 10-bit, 40 MS/s mode and 49.2 dB SNDR with only 7.9 mW power consumption in 8-bit, 2.5 MS/s mode. The area of the core layout is 1.9 mm2 in a 0.35 μm bulk-CMOS process.

Low-power sensor signal monitoring and impulse radio architecture for biomedical applications

Remote diagnostics of the vital information of a patient and the initiation of necessary actions by the healthcare professionals have resulted in the development of wireless body area network (WBAN). With little to no maintenance, each sensor node within a WBAN must operate with less than 100 μW of power consumption. Impulse radio architecture can be utilized to achieve this goal. This paper reports a low-power transmitter unit consisting of a Data Generator Block, an Impulse Generator Block and a Buffer. The Data Generator Block converts any electrochemical sensor current ranging from 0.2 to 2 μA to digital data. This block consumes a power in the range of 2.575---4.29 μW. The Impulse Generator Block utilizes an RC network to generate impulses of approximately 55 ns duration. Both the Data Generator Block and the Impulse Generator Block can operate with a 1 V supply. Finally, a Buffer circuit, which operates with a 2 V supply, is used to drive a standard 50 Ω load such as an external antenna. The peak current consumption of the impulses is 2.11 mA with a peak output voltage of 72 mV, making it extremely suitable for short range wireless communication. The entire system has been designed and fabricated using a 90 nm standard CMOS process. The average power consumption of the system is only 22.10 μW.

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.

Comparative study of sub-volt differential difference current conveyors

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limit their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG)* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at ±300mV supply voltage and 18.5µW power consumption. The simulation results using 0.18µm CMOS n-Well process from TSMC show the features of the proposed circuits.

A Novel Low-Effort Demodulator for Low Power Short Range Wireless Transceivers

This paper presents a novel demodulator architecture for short distance communication application with low effort, which is low-power low-cost while achieving robust and sufficient performance. Compared to other architectures, power consumption and design complexity are significantly reduced. Practical issues such as image interference, group delay and frequency offset are compensated and calibrated in the proposed architecture. Simulation results show that with the proposed techniques the receiver gains significant robustness against image interference, and also higher immunity to the noise and the frequency mismatches. This demodulator circuit is fully integrated in 130 nm CMOS technology, and occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area with 3.4 mW of power consumption.

A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection

This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc(3) filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86- μVrms input-referred noise, and 2.4- μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48- μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588- μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6- μm CMOS process. The die size is 11.25 mm(2).

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

This paper presents the architecture of a 10b 170 MS/s two-step binary-search assisted time-interleaved SAR ADC. The front-end stage of this ADC is built with a 5b binary-search ADC, which is shared by two time-interleaved 6b SAR ADCs in the second-stage. The design does not use any static component such as op-amp or preamplifier that causes large dissipation of static power. DAC settling speed and power are also relaxed thanks to this architecture. Besides, the process insensitive asynchronous logic further reduces the delay of SA loop rather than using worst case delay cells to compensate the process variation problem. The ADC was fabricated in 65 nm CMOS and achieves 54.6 dB SNDR at 170 MS/s with only 2.3 mW of power consumption, leading to a FoM of 30.8 fJ/conversion-step.

Wireless Recording Systems: From Noninvasive EEG-NIRS to Invasive EEG Devices

In this paper, we present the design and implementation of a wireless wearable electronic system dedicated to remote data recording for brain monitoring. The reported wireless recording system is used for a) simultaneous near-infrared spectrometry (NIRS) and scalp electro-encephalography (EEG) for noninvasive monitoring and b) intracerebral EEG (icEEG) for invasive monitoring. Bluetooth and dual radio links were introduced for these recordings. The Bluetooth-based device was embedded in a noninvasive multichannel EEG-NIRS system for easy portability and long-term monitoring. On the other hand, the 32-channel implantable recording device offers 24-bit resolution, tunable features, and a sampling frequency up to 2 kHz per channel. The analog front-end preamplifier presents low input-referred noise of 5 μ VRMS and a signal-to-noise ratio of 112 dB. The communication link is implemented using a dual-band radio frequency transceiver offering a half-duplex 800 kb/s data rate, 16.5 mW power consumption and less than 10(-10) post-correction Bit-Error Rate (BER). The designed system can be accessed and controlled by a computer with a user-friendly graphical interface. The proposed wireless implantable recording device was tested in vitro using real icEEG signals from two patients with refractory epilepsy. The wirelessly recorded signals were compared to the original signals recorded using wired-connection, and measured normalized root-mean square deviation was under 2%.

Ultra-low-power radiation hard ADC for particle detector readout applications

Radiation hard analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130 nm CMOS process and it achieves 12-bit resolution, 25 MS/s sampling speed, 15 mW power consumption and hardness to at least 1.8 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The readout of the Liquid Argon Calorimeter of the ATLAS detector in the planned High-Luminosity Large Hadron Collider is one possible application for this ADC.

Low complexity lossless compression of underwater sound recordings

Autonomous listening devices are increasingly used to study vocal aquatic animals, and there is a constant need to record longer or with greater bandwidth, requiring efficient use of memory and battery power. Real-time compression of sound has the potential to extend recording durations and bandwidths at the expense of increased processing operations and therefore power consumption. Whereas lossy methods such as MP3 introduce undesirable artifacts, lossless compression algorithms (e.g., flac) guarantee exact data recovery. But these algorithms are relatively complex due to the wide variety of signals they are designed to compress. A simpler lossless algorithm is shown here to provide compression factors of three or more for underwater sound recordings over a range of noise environments. The compressor was evaluated using samples from drifting and animal-borne sound recorders with sampling rates of 16-240 kHz. It achieves >87% of the compression of more-complex methods but requires about 1/10 of the processing operations resulting in less than 1 mW power consumption at a sampling rate of 192 kHz on a low-power microprocessor. The potential to triple recording duration with a minor increase in power consumption and no loss in sound quality may be especially valuable for battery-limited tags and robotic vehicles.

Highly linear wide‐swing continuous tuning of CMOS transconductors

SUMMARYA technique to improve the input and output range of CMOS transconductors with resistive current division for continuous tuning is presented. Using it, a tunable transconductor is proposed which features high linearity over a wide input range and simplicity. Measurement results of the transconductor, fabricated in a 0.5 µm CMOS process, show an IM3 of −66 dB for a ±1.65 V supply and two input tones centered at 1 MHz of 1 Vpp each, and only 0.7 mW of power consumption. This represents an improvement of 13 dB versus the same transconductor using conventional current division. Copyright © 2013 John Wiley &amp; Sons, Ltd.

Optimization and implementation of the wavelet based algorithms for embedded biomedical signal processing

Existing biomedical wavelet based applications exceed the computational, memory and consumption resources of low-complexity embedded systems. In order to make such systems capable to use wavelet transforms, optimization and implementation techniques are proposed. The Real Time QRS Detector and ?De-noising? Filter are developed and implemented in 16-bit fixed point microcontroller achieving 800 Hz sampling rate, occupation of less than 500 bytes of data memory, 99.06% detection accuracy, and 1 mW power consumption. By evaluation of the obtained results it is found that the proposed techniques render negligible degradation in detection accuracy of -0.41% and SNR of -2.8%, behind 2-4 times faster calculation, 2 times less memory usage and 5% energy saving. The same approach can be applied with other signals where the embedded implementation of wavelets can be beneficial.

Design and Performance Evaluation of a 10GHz 32nm-CNTFET IR-UWB Transmitter for Inter-Chip Wireless Communication

In this paper, we have presented the design and performance evaluation of a 10GHz 32nm-CNTFET IR-UWB transmitter for inter-chip wireless transmission. We have designed the transmitter using a VCO-based high speed clock generator and a positive and a negative monocycle Gaussian pulse generator. RF compatible Carbon Nano-Tube Field Effect Transistors (CNTFETs) have been used as the building blocks of the oscillator and the logic gates. The final design has resulted to a 7-channel-SWNT CNTFET-based transmitter for optimum 10GHz data rate with a promising 650mV pulse amplitude and only 1.069mW power consumption with a -32.27dB output. This transmitter can also operate satisfactorily upto 15GHz. The results show promising superiority over existing transmitters regarding high data rate, low power loss and high pulse amplitude.

Current‐reuse single Miller feedforward compensation for multi‐stage amplifiers

Presented is a novel current-reuse single Miller feedforward compensation (CRSMFC) scheme for multi-stage operational amplifiers (opamps). The proposed scheme introduces an implicit feedforward path into an opamp by reusing the current of the input stage, which creates a left-half-plane zero to cancel out the first non-dominant pole in the transfer function, thus improving phase margin and gain bandwidth product (GBW) without extra power consumption. A three-stage opamp prototype with proposed CRSMFC is realised in standard 0.18 µm CMOS process, and measured results show that it achieves a GBW of 4.4 MHz and a phase margin of 73° while driving a large capacitive load of 250 pF with only 34 µW of power consumption, implying a superior FoM over the state-of-the-art.