mW Power Consumption Research Articles

A Compact, Dual Channel Flow-based Differential Pressure Sensor with mPa Resolution and Sub-10 mW Power Consumption

In this work, we propose a single-chip sensor for the detection of two extremely low, independent differential pressures. The operating principle consists in measuring the airflow induced by the pressure through a channel of sub-millimeter cross-section [1]. The airflow is measured by differential thermal flow sensors, implementing a recently proposed drift-free offset compensation approach. Use of a low-noise, low-power readout interface, integrated on the same chip as the sensing structures, allowed the achievement of resolutions of 1.29 mPa, which are one order of magnitude lower than state-of-art devices. This performance has been obtained with power consumptions suitable for battery-powered applications.

V‐band 18.3 dB/1.6 dBm three‐stage amplifier with inductive self‐biasing in 130‐nm CMOS

ABSTRACTThe common source amplifier design with the inductive self‐biasing is presented. The proposed design can establish the biasing and the impedance matching with two transmission line elements. Both theoretical and experimental verifications confirm that the three‐stage prototype achieves a gain per stage of 6.1 dB, and the output P1dB of 1.6 dBm with 29 mW power consumption at 53 GHz based on the standard CMOS 130 nm 1P8M technology. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:409–413, 2016

Design and Optimization of Ultra Low Power Low Noise Amplifier using Particle Swarm Optimization

In this paper, an Inductively Degenerated Cascode Low Noise Amplifier (IDCLNA) is designed using TSMC 0.13 μm RF CMOS technology. For improving the performances of LNA, modifications are done in conventional IDCLNA. They are 1. Forward Body Bias (FBB) technique is applied to reduce the supply voltage. 2. The inductor is added between main and cascode transistors for increasing the gain. 3. To reduce the noise factor of cascode stage, an inductor is inserted at the gate of cascode stage. 4. For improving the stability factor, the modified resistive and capacitive shunt feedback is used. The proposed LNA produces 10.7 dB voltage gain, 3.27 dB noise figure, -9.1 dBm IIP3 and 957 μW power consumption. For optimizing the design parameters of proposed LNA, the popular optimization technique like Particle Swarm Optimization (PSO) algorithm is used to improve the performance measures. The optimized LNA achieves 12.6 dB voltage gain, 3.19 dB noise figure and consumes 869 μW power. The optimized results produce the good Figure of Merit (FOM) of 6.6. Keywords: Figure of Merit, LNA, Power Consumption and PSO

A 1.36 μW 312–315 MHz synchronized-OOK receiver for wireless sensor networks using 65 nm SOTB CMOS technology

The paper presents a receiver design operating at 312–315MHz frequency band for wireless sensor networks. The proposed architecture uses synchronized on–off-keying (S-OOK) modulation scheme, which includes clock information together with data, providing self-synchronization ability for the receiver without a separate clock and data recovery circuit. In addition, a new technique is also proposed to reduce active time of the RF font-end for better energy efficiency. The receiver architecture is verified by using discrete RF modules and FPGAs, then VLSI design is carried out on 65nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology and simulated using SPICE models to illustrate effectiveness of the proposed architecture. Post-layout simulation shows −58.5dBm sensitivity with 1.36μW and 8.39μW power consumption corresponding to 10kbps and 100kbps data rate, respectively.

TOFPET 2: A high-performance circuit for PET time-of-flight

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Small area 0.3 pJ/conv, 45 ps time‐to‐digital converter for arrays of silicon photomultiplier interfaces in 150 nm CMOS

A ring-oscillator-based time-to-digital converter (TDC) is presented which can achieve a figure-of-merit of 0.3 pJ/conv in a very small footprint of 0.0024 mm2. Thanks to the optimisation of the ring-oscillator and of the sub-cycle interpolation, a 45-ps LSB is obtained with only 0.95 mW of power consumption. The area and power characteristics make the TDC suitable for its use in repeated instances, such as in multiple silicon photomultipliers readout channels or single-photon imaging devices with time-correlated detection.

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

A 3 MHz-to-1.8 GHz, 94 $\mu\hbox {W}$ -to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses the same type of delay lines for cyclic delay determination and coarse locking is proposed and used to achieve the design goals of small footprint and fast locking for a large operating frequency range. In addition, a new delay structure is developed for the cyclic delay units and coarse delay line. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, the automatic bypassing of the cyclic operation is developed and used to reduce power consumption during high-frequency operation. Through the use of proposed techniques, the active area is reduced to only 0.0153 mm $^{2}$ , and the operating frequency range is from 3 MHz to 1.8 GHz. The measurement results show that the proposed ADDLL achieves a peak-to-peak jitter of 3 ps with 9.5 mW power consumption when operated at 1.8 GHz.

A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor

A marker-less camera pose estimation engine (CPEE) with reconfigurable logarithmic SIMD processor is proposed for the view angle estimation used in mobile augmented reality (AR) applications. Compared to previous marker-based approach, marker-less camera pose estimation can overlay virtual images directly on natural world without the help of markers. However, they require 150x larger computing costs and large power consuming floating-point operations where such requirement severely restricts real-time operations and low-power implementations in mobile platform, respectively. To overcome the gap in computational costs between marker-based and marker-less method, speculative execution (SE) and reconfigurable data-arrangement layer (RDL) are proposed to reduce computing time by 17% and 27%, respectively. For low-power implementation of floating-point units, logarithmic processing element (LPE) is designed to reduce overall power consumption by 18%. The proposed marker-less CPEE is fabricated in 65 nm Logic CMOS technology, and successfully realizes real-time marker-less camera pose estimation with only 27 mW power consumption.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

A Versatile Embedded Platform for EMG Acquisition and Gesture Recognition.

Wearable devices offer interesting features, such as low cost and user friendliness, but their use for medical applications is an open research topic, given the limited hardware resources they provide. In this paper, we present an embedded solution for real-time EMG-based hand gesture recognition. The work focuses on the multi-level design of the system, integrating the hardware and software components to develop a wearable device capable of acquiring and processing EMG signals for real-time gesture recognition. The system combines the accuracy of a custom analog front end with the flexibility of a low power and high performance microcontroller for on-board processing. Our system achieves the same accuracy of high-end and more expensive active EMG sensors used in applications with strict requirements on signal quality. At the same time, due to its flexible configuration, it can be compared to the few wearable platforms designed for EMG gesture recognition available on market. We demonstrate that we reach similar or better performance while embedding the gesture recognition on board, with the benefit of cost reduction. To validate this approach, we collected a dataset of 7 gestures from 4 users, which were used to evaluate the impact of the number of EMG channels, the number of recognized gestures and the data rate on the recognition accuracy and on the computational demand of the classifier. As a result, we implemented a SVM recognition algorithm capable of real-time performance on the proposed wearable platform, achieving a classification rate of 90%, which is aligned with the state-of-the-art off-line results and a 29.7 mW power consumption, guaranteeing 44 hours of continuous operation with a 400 mAh battery.

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

A coarse-grained reconfigurable processing unit (RPU) consisting of 16 ×16 multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a 5.4 mm ×3.1 mm die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920 ×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3 × improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720 ×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96 × improvement on energy efficiency compared with the ADRES reconfigurable processor.

Novel Q‐factor enhancement technique for on‐chip spiral inductors and its application to cmos low‐noise amplifier designs

ABSTRACTIn this article, a novel Q‐factor enhancement technique for on‐chip spiral inductors is presented. Symmetric return ground structure in traditional on‐chip spiral inductors is modified and shifted toward the side with stronger magnetic field caused by asymmetrical windings of inductors. In full‐wave electro‐magnetic simulation, it is observed that by applying this technique, inductor with higher Q‐factor and larger inductance is obtained with no cost of additional chip area. Using the proposed technique, on‐chip inductors are customized for a three‐stage cascode low‐noise amplifier (LNA) design. Fabricated in a commercial 65‐nm CMOS process, the LNA features peak gain of 26.3 dB, 21.8 mW power consumption, noise figure of 5.3 dB, output P1 dB of −4 dBm, and core size of 0.15 mm2. In the comparison with prior arts, the proposed design achieves the highest gain and figure‐of‐merit. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2883–2886, 2015

Electronically Tunable Current-mode High-order Ladder Low-pass Filters Based on CMOS Technology

This paper describes the design of current mode low-pass ladder filters based on CMOS technology. The filters are derived from passive RLC ladder filter proto- types using new CMOS lossy and lossless integrators. The all-pole and Elliptic approximations are used in the pro- posed low-pass filter realizations. The proposed two types of filter can be electronically tuned between 10 kHz and 100 MHz through bias current from 0.03 µA to 300 µA. The proposed filters use 1.5 V power supply with 3 mW power consumption at 300 µA bias current. The proposed filters are resistorless, use grounded capacitors and are suitable for further integration. The total harmonic distor- tion (THD) of the low-pass filters is less than 1% over the operating frequency range. PSPICE simulation results, obtained by using TSMC 0.18µm technology, confirm the presented theory.

60 GHz CMOS gain‐boosted LNA with transformer feedbacked neutraliser

A 60 GHz low-noise amplifier (LNA) using standard 65 nm CMOS technology is presented. A gain of the 60 GHz amplifier was boosted by using a transformer feedbacked capacitor neutraliser. To stabilise the process variations caused by the positive feedback system, the body node of the triple well was adjusted to tune the capacitor value. The theory, simulation and measurements are presented. An implementation prototype is evaluated using on-wafer proving. The LNA showed a measured peak gain of 30 dB and a measured noise of 4.6 dB under 8.9 mW power consumption with a 1 V supply voltage. The measured IIP3 was −26 dBm. This is believed to be the first CMOS 60 GHz LNA to compensate the overlap capacitor with a single-ended structure.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs

This brief presents an energy-efficient high-speed digital-to-analog converter structure that is implemented in a 10-bit 150-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce energy consumption and improve ADC linearity, a segmented prequantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of prequantization. To eliminate possible conversion error caused by parasitic capacitance and provide redundancy, two extra capacitors are inserted. A prototype 10-bit 150-MS/s SAR ADC with the proposed architecture is implemented in a standard 65-nm CMOS technology. According to the simulation, the ADC achieves a spurious-free dynamic range of 83.64 dB and an effective number of bits of 9.52 bits with only 1.20 mW power consumption at a 1.2-V supply, resulting in a figure of merit of 10.9 fJ/conversion-step.

A Startup Robust Feedback Class-C VCO With Constant Amplitude Control in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m CMOS

A feedback class-C VCO with constant amplitude control is presented in this letter. Its dual-loop topology helps to stabilize amplitude and ensure startup robustness over process, voltage and temperature (PVT) variations. Besides, this VCO facilitates a direct amplitude calibration method to find optimal point for different applications. A prototype VCO is implemented in a 0.18 $\mu$ m CMOS process. Measurement shows the VCO has a 4.55–5.16 GHz frequency tuning range and a phase noise of ${-}123.3$ dBc/Hz at 1 MHz offset from a 5 GHz carrier with a 2.78 mW power consumption. The FOM is ${-}192.8$ dBc/Hz.

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of $$\mathrm{VDD}=1.8$$VDD=1.8 v in 180 nm CMOS technology for 64- and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz with 1.604 mW power consumption. Our designs are proper for reconfigurable and multi-standard ADPLL designs.

44 pJ/bit energy‐efficiency K‐band OOK transmitter for wireless sensor networks

A high energy-efficiency K-band on–off keying (OOK) transmitter in tsmc™ 90 nm CMOS technology is presented. The transmitter consists of a wideband voltage control oscillator (VCO), a frequency doubler and a switch-type power amplifier with a chip area of 0.6 × 0.92 mm2. The VCO adopts a parasitic capacitance reduction technique to enhance the tuning range to 20.5%. The designed transmitter achieves an output power of 3 dBm with a 500 Mbit/s data rate from 19 to 23.1 GHz at 22.3 mW power consumption. The correspondent energy-efficiency is 44 pJ/bit.