mW Power Consumption Research Articles

An Inverter-Based, CMOS, Low-Power Optical Receiver Front-End

ABSTRACTIn this paper, a low-power optical receiver front-end which consists of a transimpedance amplifier (TIA) and three stages of limiting amplifier (LA) for 2.5 Gb/s applications is proposed in 0.18 µm CMOS technology. The proposed TIA benefits from a modified inverter structure, in which the input resistance is properly reduced due to the use of diode-connected transistors in comparison with conventional inverter circuit. Also, an active inductor is used in parallel with a diode-connected transistor at the output node, which provides a low output resistance, while it resonates with the load capacitance to extend the −3 dB frequency bandwidth. Moreover, three stages of LAs are used to obtain extra gain, in which each LA cell uses active inductor load. However, HSPICE simulations for the proposed TIA circuit show a 42.24 dBΩ transimpedance gain, 1.96 GHz frequency bandwidth, 11.7 pA/√Hz input referred noise, and only 972 µW of power consumption at 1.5 V supply. Also, simulation results for the whole receiver system show a 75.6 dB gain, 1.7 GHz frequency bandwidth, and 6.54 mW of power consumption at 1.5 V supply. Finally, simulation results indicate that the proposed receiver system has good performances to be used as a low-power optical receiver front-end.

28 GHz GaAs pHEMT MMICs and RF front‐end module for 5G communication systems

AbstractThis article presents a 28 GHz switch and LNA chipset, and the RF front‐end module for 5G communication systems. The 28 GHz Single Pole Double Through (SPDT) switch and LNA MMICs are embedded in single RF front‐end module successfully using molding based embedded Wafer‐Level Package (eWLP) technology. For the low noise figure and high isolation, inductive source degenerated LNA topology and double shunt FET structure for SPDT switch are employed, and LNA and SPDT are implemented in single IC. The eWLP based package minimizes the parasitic component such as bond‐wire inductance and signals loss to enhance the performance of the RF front‐end module. At 28 GHz, the measured gain and noise figure of receiver path are 15.5 dB and 3.46 dB, respectively, and the IIP3 is +3 dBm at 45 mW power consumption.

A 24/77 GHz Dual-Band Receiver for Automotive Radar Applications

A fully-integrated 24/77 GHz dual-band receiver is presented for automotive radar applications. The proposed receiver consists of a dual-band LNA, a dual-band sub-sampling PLL, and a wideband mixer, operating at 24 and 77 GHz alternatively. Implemented in 65 nm CMOS technology, the receiver achieves 760 and 1800 MHz bandwidth with 52 and 60 mW power consumption in 24 and 77 GHz operation modes, respectively. To the best of authors' knowledge, this is the first fully-integrated CMOS 24/77 GHz dual-band receiver for automotive radar applications.

NALoc

Visible light position (VLP) is a revolutionary technique which enables many promising applications. As the human eye is sensitive to low-rate changes, VLP systems often convey location information through light flickering over 1 KHz, which induces a heavy burden on the VLP receiver. Existing solutions either rely on the high-resolution cameras or a dedicated photodiode to capture the location information, but the high power consumption and extraction deployment cost hinder their wide adoption. In this paper, we present a light-weight VLP system, NALoc, which leverages the ambient light sensor (ALS) readily on many mobile devices to sense high-frequency-modulation location information. To overcome the insufficient sampling ability of ALS, we exploit the nonlinearity of ALS to sense the leaked energy from high frequency(≥ 1 KHz) at a low sampling rate(100 Hz). Extensive evaluations demonstrate that our system can achieve a decimeter-level localization accuracy with about 1 mW power consumption, which is 2000 times less than existing camera-based VLP solutions.

A high performance 19.2MHz digitally controlled crystal oscillator for NB-IoT

This design implements a 19.2MHz digitally controlled crystal oscillator (DCXO) for the narrow-band internet of things system (NB-IoTs). The paper uses positive feedback principle and phase analysis method to design the oscillator, and then the circuit is realized in a 55nm CMOS technology. The DCXO frequency is controlled by a capacitor matrix controlled by a 10bit digital signal. The results show that the crystal tunable range is more than 70ppm, with tuning step of 0.1∼0.2ppm. The phase noise in 1 KHz and 10 KHz offset were -137dBc/Hz and -159dBc/Hz, respectively. The maximum power consumption is 0.72mW at 1.2V power supply voltage, including an output buffer with 0.24mW power consumption.

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

Towards eco-friendly power sources: In series connected glucose biofuel cells power a disposable ovulation test

A disposable ovulation test is operated using a flow stack of 5 in series connected glucose biofuel cells giving an open circuit voltage (OCV) of 3.5 V. Such tests consume at total around 60 μWh of energy and in average 1.7 mW of power during one run of around 12 min which are supplied by a CR1220 3 V lithium button battery in the commercialized device. We replaced this battery by the glucose biofuel cell stack and observed during the measurements and display steps peak currents up to 1.4 mA inducing a voltage drop down to 2.8 V during few seconds (4 mW of power consumption). Even such power peaks are supported by the presented biofuel cell stack assuring the necessary operational cell voltage and current. After the measurements towards Luteinizing Hormone (LH) detection the display remains turned on for 8 min and consumes just 2 μW which allows to reestablish the initial OCV and to run a further test. The presented results demonstrate as proof of concept the suitability of eco-friendly enzymatic glucose biofuel cells as alternative power source for disposable devices.

CMOS Monolithic Electrochemical Gas Sensor Microsystem Using Room Temperature Ionic Liquid.

The growing demand for personal healthcare monitoring requires a challenging combination of performance, size, power, and cost that is difficult to achieve with existing gas sensor technologies. This paper presents a new CMOS monolithic gas sensor microsystem that meets these requirements through a unique combination of electrochemical readout circuits, post-CMOS planar electrodes, and room temperature ionic liquid (RTIL) sensing materials. The architecture and design of the CMOS-RTIL-based monolithic gas sensor are described. The monolithic device occupies less than 0.5mm2 per sensing channel and incorporates electrochemical biasing and readout functions with only 1.4mW of power consumption. Oxygen was tested as an example gas, and results show that the microsystem demonstrates a highly linear response (R2 = 0.995) over a 0 - 21% oxygen concentration range, with a limit of detection of 0.06% and a 1 second response time. Monolithic integration reduces manufacturing cost and is demonstrated to improve limits of detection by a factor of five compared to a hybrid implementation. The combined characteristics of this device offer an ideal platform for portable/wearable gas sensing in applications such as air pollutant monitoring.

Efficient DSP and Circuit Architectures for Massive MIMO: State of the Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.

RF Bandaid

This paper presents a passive wireless RF sensor platform (RFSP), with only analog components, that harvests energy from an RF source and reflects data as a direct subcarrier modulation, thus making it battery free. A fully-analog architecture results in an ultra-low power device (under 200 μW) with a low component count, reducing the physical footprint. We envision such a platform to enable medical sensing systems that fit on a small bandaid like flexible structure, require no-battery, or charging and are able to provide continuous physiological monitoring. To realize this vision, we have developed and optimized a novel RF architecture that 1) directly maps sensor output to frequency modulation and transmits it to a remote receiver processing unit (RPU). This direct frequency mapping allows all further digitization and computation to be moved to the RPU -- reducing power and size requirements on the RFSP; 2) harvests energy from the carrier signal transmitted by a simple continuous wave transmitter, thereby requiring no batteries or supercap; and 3) uses backscatter to communicate with the RPU enabling ultra-low power requirements. The total power consumption of our prototype device leveraging this architecture was measured to be between 35 μW and 160 μW. We demonstrate that the RFSP can harvest sufficient power, sense, and communicate continuously without necessity for energy storage at a distance of 4 m from a transmitter emitting a 915 MHz continuous wave at 26 dBm (0.39 W). Prior backscatter systems typically have power budgets of 1 mW and require energy storage (battery or supercap), RFSP's sub 200 μW power consumption provides a significant improvement and longer range for a given TX power. To demonstrate applicability to real-world health sensing and the flexibility to adapt to different sensors, this paper presents results from breathing, heart rate, temperature, and sound sensing applications.

Scalable cryogenic readout circuit for a superconducting nanowire single-photon detector system.

The superconducting nanowire single-photon detector (SNSPD) is a leading technology for quantum information science applications using photons, and is finding increasing uses in photon-starved classical imaging applications. Critical detector characteristics, such as timing resolution (jitter), reset time, and maximum count rate, are heavily influenced by the readout electronics that sense and amplify the photon detection signal. We describe a readout circuit for SNSPDs using commercial off-the-shelf amplifiers operating at cryogenic temperatures. Our design demonstrates a 35 ps timing resolution and a maximum count rate of over 2 × 107 counts per second, while maintaining <3 mW power consumption per channel, making it suitable for a multichannel readout.

Optically triggered global shutter image sensor using single‐photon avalanche diodes

A novel optically triggered global shutter image sensor using single photon avalanche diodes (SPAD) is proposed. An optical signal with a switching frequency of 100 MHz illuminates SPADs and acts as both a shutter and reset signal source by means of free space optics. Each image sensor pixel contains a front side illuminated SPAD, while a pinned photodiode is used to collect the scene's light from the chip back side to increase the pixel fill factor. The pixel is designed and post layout simulated in 90 nm complementary metal oxide semiconductor technology. Moreover, the jitter performance of 76.2 ps (excluding SPAD and light source jitter) is achieved. The image sensor pixel pitch is 90 µm with 2.27 mW power consumption per pixel with a fill factor of above 90%. The image sensor pixel can take 64 different frames at the rate of 50 Mfps and store until the global readout phase.

Phase noise model of ring oscillator under reduced supply with application to a time to digital converter

This paper investigates the phase noise of voltage controlled ring oscillators. The delay cell is a differential pair with no tail current source, suitable for reduced supply voltage as technology scales. As N, number of stages, decreases, the output can become unsaturated, introducing extra correlation and adding phase noise. The new phase noise model is developed (focusing on N = 2), which improves on impulse sensitivity function, Using a 0.13 μm CMOS technology in 1.2 V supply, this model is applied to the delay cell under different circuit parameters (focusing on tuning) and operating conditions, with theoretical results agreeing with simulations. The design was fabricated in 0.13 μm CMOS, and operates at 0.89 GHz oscillator frequency, and has 200 μW power consumption. To study the phase noise when the VCO is tuned, measurements at the boundary of typical tuning range is performed and agree with theory and simulations. Insights, based on theory, are presented and explain trends of simulated and measured phase noise. Next the ring oscillator is applied to a time to digital converter (TDC). Using the above noise model, the jitter of the VCO is calculated and then apply to calculate the resulting jitter in the TDC. Then the TDC is simulated with Matlab, with VCO jitter injected, and find reasonable comparison with theory.

A rail-to-rail constant-gm CCII for Instrumentation Amplifier applications

We here present a current mode Instrumentation Amplifier (IA) based on second generation current conveyor (CCII) with complete input/output dynamic range (rail-to-rail) and constant-gm characteristics. The IA operates at 1.5 V supply with 177 μW power consumption, high-loop gain (115 dB) and high CMRR (105 dB). The proposed IA has been implemented by using a standard AMS 0.35-μm CMOS technology. SPICE simulations are also reported.

Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance. For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss &lt;-13 dB and 12.5 mW power consumption.

Linearisation technique for low‐voltage tuneable Nauta's transconductor in G m − C filter design

A low-distortion, low-voltage transconductor based on Nauta's inverter-type transconductor is proposed. The transconductor's core MOSFETs are pushed into a strong inversion region under a low-voltage supply utilizing a level shifter consisting of a linear resistor and a MOSFET current source. The transconductor's linearization relies on summing a decreasing G m characteristic with an increasing counterpart to obtain an overall flat G m characteristic. The non-ideal decreasing G m is exploited from a non-linear behaviour of the triode-MOS current source that restricts a | V GS | increment of the core strongly-inverted MOSFET quartet while its increasing- G m counterpart found in another weakly-inverted auxiliary MOSFET quartet. The MOSFET current source plays significant role in the linearization process where it has to be in a triode mode of either a strong, weak or moderate inversion region. Simulation results are provided to verify the feasibility of the proposed transconductor with a 5th-order Chebyshev lowpass filter in a 0.18 μm CMOS process. The filter operates under a 0.5 V supply (the ratio V DD / V TH = 1.19) with a continuous bandwidth tuning from 500 kHz to 2.8 MHz. The proposed filter with a nominal 1.4 MHz bandwidth and a 430 mW power consumption renders the two-tone SFDR of 64.9 dB.

A 0.6V, 8.4uW AFE circuit for biomedical signal recording

For the detection of biomedical signal in wearable health devices, in this paper a fully-integrated, low-power, low-noise analog front-end (AFE) circuit is proposed. The AFE circuit includes a fully-differential amplifier with high-pass characteristics and a 14bit/500 Hz Sigma-Delta modulator based on cascode inverter. The fully-differential amplifier increases the output swing and improves the signal to noise ratio (SNR). Inverter-based Sigma-Delta modulator using bootstrapped switch completes high accuracy signal sampling in low supply voltage and finally outputs digital code. Two subthreshold bandgaps provide stable bias current and reference voltage for amplifier and Sigma-Delta modulator respectively. The circuit is fabricated with SMIC 0.13 μm CMOS mixed-signal technology occupying area of 1.68 mm2. The measurement results show that when the power supply voltage is 0.6 V, the input referred voltage noise of amplifier is 3.976μVrms and noise efficient factor (NEF) is 3.658. The maximum signal to noise and distortion ratio (SNDR) of AFE is 66.7 dB with only 8.4μw power consumption. Compared with the previous references, it has the maximum SNDR among them.

A low phase noise gm-boosted DTMOS VCO design in 180 nm CMOS technology

This paper presents the design of a low phase noise voltage controlled oscillator (VCO), which offers higher transconductance (gm) by the use of parallel MOSFETs. Here, two NMOS transistors are connected in parallel with the cross-coupled NMOS transistors of a conventional cross-coupled VCO. So, the total negative conductance offered to the circuit to cancel out the parasitic resistance of the LC-tank is increased. This negative conductance is achieved without dealing with larger transistor size or any other passive elements. Hence, power dissipation and silicon area are reduced. Further, dynamic threshold MOSFET (DTMOS) with a capacitive division technique is implemented to increase the voltage swing, leading to a further decrease in phase noise. The proposed VCO is designed and simulated in UMC 180 nm technology. It achieves a tuning range of 1.58–1.60 GHz about 200 MHz, with 6.09 mW power consumption at 1.1 V supply voltage. The phase noise is obtained −40.6 dBc/Hz at 1 kHz and −120.44 dBc/Hz at 1 MHz respectively. So, it should be used in transceiver and PLL blocks for low voltage and low phase noise applications.