mW Power Consumption Research Articles

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.

Low cost wireless current sensor for NIALM application

This paper presents a low cost wireless current sensor dedicated to Non-Intrusive Appliance Load Monitoring (NIALM) application. Thanks to the requirement of such technology, two kinds of sensor are studied and realized: one for transient measurement and one for steady-state measurement. Using NIALM algorithms, the transient sensor allows us to determine event detection (On/off operation), while the second one is dedicated to signature analysis and power consumption estimation in order to classify appliances.New design of current sensor, including theoretical analysis and simulation, is presented. The performances of this new Rogowski coil sensor are measured and compared with a commercial product. Finally, a low power transmitter, based on a simple ramp Analog-to-Digital Converter architecture and a PWM-OOK modulation, is proposed and designed in 180nm CMOS technology. The post-layout simulation exhibits a 1.8mW power consumption for an output power of −10dBm.

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI

This work demonstrates a self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor. A tunable replica circuit (TRC) composed of inverter cells from the standard-cell library performs real-time frequency modulation to reduce the response time to a single cycle, and a digital controller quantizes the clock frequency by selecting appropriate phases of a delay-locked loop (DLL) that generates 16 phases of 2 GHz output. A watchdog unit continuously monitors the clock output to guard against metastability arising from the asynchronous path between the controller and the DLL. The proposed design is implemented in a 28 nm UTBB FDSOI technology and occupies an area of 1120 $\mu \text {m}^{2}$ with 2.7 mW power consumption. The generator has a wide tuning range of 550–2260 MHz at 1 V, functions at 35 MHz at 0.4 V, and can continuously synthesize the clock signal for arbitrary voltage waveforms between 0.4 V and 1 V.

Two‐step injection clock generation technique for fractional‐ N MDLL

Two-step injection clock generation technique is presented for fine resolution fractional-N multiplying delay-locked loop (MDLL). The coarse DLL generates multiple coarse clock phases, and then fine DLL performs fine phase control for MDLL injection clock. The proposed technique is applied to fractional-N MDLL and efficiently achieves 8b fractional frequency resolution. The MDLL designed in a 0.18 μm CMOS process occupies 0.065 mm2 and generates 10 MHz frequency with 61 μW power consumption.

Planar Indium Tin Oxide Heater for Improved Thermal Distribution for Metal Oxide Micromachined Gas Sensors.

Metal oxide gas sensors with integrated micro-hotplate structures are widely used in the industry and they are still being investigated and developed. Metal oxide gas sensors have the advantage of being sensitive to a wide range of organic and inorganic volatile compounds, although they lack selectivity. To introduce selectivity, the operating temperature of a single sensor is swept, and the measurements are fed to a discriminating algorithm. The efficiency of those data processing methods strongly depends on temperature uniformity across the active area of the sensor. To achieve this, hot plate structures with complex resistor geometries have been designed and additional heat-spreading structures have been introduced. In this work we designed and fabricated a metal oxide gas sensor integrated with a simple square planar indium tin oxide (ITO) heating element, by using conventional micromachining and thin-film deposition techniques. Power consumption–dependent surface temperature measurements were performed. A 420 °C working temperature was achieved at 120 mW power consumption. Temperature distribution uniformity was measured and a 17 °C difference between the hottest and the coldest points of the sensor at an operating temperature of 290 °C was achieved. Transient heat-up and cool-down cycle durations are measured as 40 ms and 20 ms, respectively.

A 10.2 mW multi-mode continuous-time ΔΣ ADC with 70–87 dB DR and 0.7–10 MHz bandwidth for TD-SCDMA and LTE digital receivers

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.

A Hybrid Topology for Frequency Divider using PLL Application

In this paper, we present a new type of odd integer divider topology which consume low power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 topologies involves only D Flip-Flops (DFF), which realized mostly Common Mode Logic DFF (CML) or True Single Phase Clock (TSPC) based DFF. These were high-speed dividers but no flexibility in this topology i.e. it divides the only power of N. So the proposed divider gives more flexibility to the topology like divided by any real odd integer. While designing a new topology the limitations are operating frequency range, a number of transistor and power consumption. Based on this consideration the 3T NAND and TSPC based Flip-Flop are investigated. The maximum operating frequency of the TSPC divide by 2 is reaches at 2.4 GHz with 1.1931 mw power consumption and is 50% low power consumption compared to the NAND_DFF based frequency divider. Similarly, divide by 3, divide by 5 and divide by 7 also consume low power with less number of transistor compare to the NAND_DFF based frequency divider. So the results show the TSPC is DFF’s more preferable for PLL application and RFIC. The TSPC_DFF based frequency divider designed using 0.18 um CMOS process technology.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

High Frequency Unity Gain Buffer in 90-nm CMOS Technology

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

A low power CMOS VCO using inductive-biasing with high performance FoM**Project supported by the National Science and Technology Major Project of China (No. 2011ZX03004-002-01).

A novel voltage-controlled oscillator (VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using time-varying phase noise theory derives closed-form symbolic formulas for the 1/f2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 μm CMOS technology. Working under a 0.3 V supply voltage with 1.2 mW power consumption, the measured phase noise of the VCO is −119.4 dBc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an FoM of 192.5 dBc/Hz.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Design of a high gain and power efficient optical receiver front-end in 0.13 μM RF CMOS technology for 10 Gbps applications

In this paper, two versions of a complete RF front-end for a 10 Gbps optical receiver are presented. The RF front-end consists of a transimpedance amplifier and a limiter amplifier. Two versions of the TIA amplifiers are proposed. The first topology has 54 dB transimpedance gain, 11.5 GHz bandwidth and has a input current noise density of only 6.8pA/Hz. The second topology is composed by a cascade os two inverters. This topology has 48 dB transimpedance gain, 11.2 GHz bandwidth, a input current noise density of 8.9pA/Hz and occupies an area of only 0.048 mm2. The limiter amplifier for both optical receivers is a five stage cherry-hooper amplifier with active inductors optimized for low power. The main amplifier has 38 dB gain, 9.8 GHz Bandwidth, 69 mW of power consumption and only 0.171 mm2 of die area. The complete RF front-end is fully integrated and has 10 GHz bandwidth. The circuits were designed in 0.13 μm RF CMOS technology. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1499–1504, 2016

A Low-Power Low-Phase-Noise VCO With Self-Adjusted Active Resistor

This letter presents a low-power low-phase-noise VCO with self-adjusted active resistor (SAAR). A pair of PMOS transistors is introduced between cross-coupled pairs and LC-tank, serving as the SAAR. When cross-coupled transistor resides in the saturation region, SAAR exhibits small resistance, enabling fast switching and suppressing flicker noise up-conversion to 1/f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise. Moreover, as cross-coupled transistor enters triode region, SAAR will adjust to larger resistance and prevent the small conducting resistance of the cross-coupled transistor degrading the quality factor of LC tank. Fabricated in a 65 nm CMOS technology, the proposed VCO demonstrates a tuning range of 5.07-6.35 GHz (22.4%) with only 0.42 mW power consumption at 0.6 V supply. The phase noise in the worst case is -40.8 dBc/Hz at 1 kHz and -111 dBc/Hz at 1 MHz, respectively.

TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

InGaZnO TFT behavioral model for IC design

This paper presents a behavioral model for amorphous indium---gallium---zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (CGS and CGD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 μW power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.

MEMS thermal flow sensors

This paper presents micromachined thermal flow sensors for measuring liquid flow down to 0.05μl/min. The sensing element is a parylene-C thin film with two thin film platinum resistors as heating and sensing elements. The sensors are integrated with AWG 24 Teflon tubing and additional two external constant resistors to form a Wheatstone bridge. In this study, we investigated the efficacy of the orifice type sensor in two configurations, vertical and horizontal. In vertical configuration, the sensor was arranged perpendicular to the flow direction. The orifice flow allows maximum heat transfer from the sensor to the flow but leads to higher flow resistance. After redesigning the geometries of the sensor, the dumbbell type thermal flow sensor was further developed. The sensor is suspended in the middle of the channel to improve thermal insulation and achieve better sensitivity. The sensors have demonstrated a flow rate resolution below 0.05μl/min. The experimental results show that the sensor has a sensitivity of 7.7mV/(μl/min) at 0.13mW power consumption and 0.05μl/min volumetric flow rates. Comparison with related literature has been made to judge how good the flow sensors developed in this study are.

Amplitude and Phase Modulation of UWB Monocycle Pulses on a Silicon Photonic Chip

We demonstrate both the amplitude and bi-phase modulation of ultrawideband (UWB) monocycle pulses using silicon microring modulator. The integrated silicon ring modulator generates the monocycle pulse train and modulates it simultaneously. By applying different driving voltages, the amplitude and phase-modulated UWB signal with a data rate of 2.5 Gb/s are achieved. The ring modulator can be thermally tuned for a free spectral range with a $\sim 50$ -mW power consumption.

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart—only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2\mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.

A Novel Differential Log-Companding Amplifier for Biosignal Sensing

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

Development of the read-out ASIC for muon chambers

A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.