A 10.2 mW multi-mode continuous-time ΔΣ ADC with 70–87 dB DR and 0.7–10 MHz bandwidth for TD-SCDMA and LTE digital receivers

Abstract

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.