Analysis of exponentially decaying pulse shape DACs in continuous-time sigma-delta modulators

Abstract

The performance of continuous-time (CT) sigma-delta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper, exponentially decaying DACs are investigated and generalized expressions are derived. In addition, another exponentially decaying DAC proposed, which can potentially achieve both good jitter immunity and amplitude efficiency. To validate the theoretical results, the proposed DAC, together with other exponentially decaying DACs, are employed in a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order 1-bit CT ΣΔ modulator test case and evaluated through behavioral simulations.