Multiplexer Logic Research Articles

Reconfigurable Operators: New Configuration Logic Blocks for Novel FPGA

For current FPGA architectures, the flne-grain programmable blocks are the most ∞exible ones. However, they bring in massive conflguration bits-stream and much performance loss. In this paper, we propose new conflguration logic blocks for the latest FPGA, a collection of Reconflgurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a speciflc function set. Considering the ∞exibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Speciflc Integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use conflguration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on conflguration bits-stream and comparable delay compared with Virtex5 FPGA.

A Radio Link Logical Relationship between and One Network Apparatus

MAC layer, a radio link control (RLC) layer and a broadcast and multicast control (BMC) layer exist in a second layer. The MAC layer maps various logical channels to various transport channels and performs logical channel multiplexing to map a plurality of logical channels to one transport channel.The MAC layer is connected to the RLC layer, which is a higher layer, through a logical channel. The logical channel is divided into a control channel for transmitting information on a control plane and a traffic channel for transmitting information on a user plane, according to the kind of transmitted information.

PERFORMANCE EVALUATION OF FULL ADDER AND ITS IMPACT ON RIPPLE CARRY ADDER DESIGN

Full adder is an essential module in the design and development of all types of processors such as digital signal processors (DSP), microprocessors etc. Adders are the nucleus element of composite arithmetic operations like addition, multiplication, division, exponentiation etc. The various full adders available are conventional CMOS full adder, parallel prefix adders, hybrid full adders, and mirror full adders, adders using transmission gates and multiplexer logic. The main goal is to compare the existing full adder circuit’s performance and to identify a Low Power Full Adder and to analyze its impact on 8-bit, 16-bit, 32-bit ripple carry adder design. Mentor Graphics IC studio tool in 180 nm technology is used to design and implement the proposed full adders and ripple carry adders.

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

Low Power Area Efficient Multiplier Using Shannon Based Multiplexing Logic

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.

Power Optimized Multiplier Using Shannon Based Multiplexing Logic

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.

100Gb/s Ethernet Inverse Multiplexing Based on Aggregation at the Physical Layer

We propose a packet-based inverse multiplexing method to allow scalable network access with a bigger-pipe physical interface. The method is based on aggregation at the physical layer (APL) that fragments an original packet-flow and distributes the fragments among an adequate numbers of physical links or networks. It allows us to share wavelengths and/or bandwidth resources in optical networks. Its technical feasibility at the speed of newly standardized 100Gb/s Ethernet (100GbE) is successfully evaluated by implementing the inverse multiplexing logic functions on a prototype board. We demonstrate super-high-definition video streaming and huge file transfer by transmitting 100GbE MAC frames over multiple 10GbE physical links via inverse multiplexing.

New dimensions in non‐classical neural computing, part II: quantum, nano, and optical

PurposeThe purpose of this paper is to introduce new non‐classical implementations of neural networks (NNs). The developed implementations are performed in the quantum, nano, and optical domains to perform the required neural computing. The various implementations of the new NNs utilizing the introduced architectures are presented, and their extensions for the utilization in the non‐classical neural‐systolic networks are also introduced.Design/methodology/approachThe introduced neural circuits utilize recent findings in the quantum, nano, and optical fields to implement the functionality of the basic NN. This includes the techniques of many‐valued quantum computing (MVQC), carbon nanotubes (CNT), and linear optics. The extensions of implementations to non‐classical neural‐systolic networks using the introduced neural‐systolic architectures are also presented.FindingsNovel NN implementations are introduced in this paper. NN implementation using the general scheme of MVQC is presented. The proposed method uses the many‐valued quantum orthonormal computational basis states to implement such computations. Physical implementation of quantum computing (QC) is performed by controlling the potential to yield specific wavefunction as a result of solving the Schrödinger equation that governs the dynamics in the quantum domain. The CNT‐based implementation of logic NNs is also introduced. New implementations of logic NNs are also introduced that utilize new linear optical circuits which use coherent light beams to perform the functionality of the basic logic multiplexer by utilizing the properties of frequency, polarization, and incident angle. The implementations of non‐classical neural‐systolic networks using the introduced quantum, nano, and optical neural architectures are also presented.Originality/valueThe introduced NN implementations form new important directions in the NN realizations using the newly emerging technologies. Since the new quantum and optical implementations have the advantages of very high‐speed and low‐power consumption, and the nano implementation exists in very compact space where CNT‐based field effect transistor switches reliably using much less power than a silicon‐based device, the introduced implementations for non‐classical neural computation are new and interesting for the design in future technologies that require the optimal design specifications of super‐high speed, minimum power consumption, and minimum size, such as in low‐power control of autonomous robots, adiabatic low‐power very‐large‐scale integration circuit design for signal processing applications, QC, and nanotechnology.

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Behavior synthesis and optimization beyond the register-transfer level require an efficient utilization of the underlying platform features. This article presents a platform-based resource binding approach based on a Distributed Register-File Microarchitecture (DRFM) , which makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. DRFM contains multiple islands, each having a local register file, a functional unit pool, and data-routing logic. Compared to the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in a substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Given the scheduling solution and resource (functional units) constraints, two novel algorithms in the resource binding stage are developed based on DRFM: (i) a simultaneous DRFM clustering and binding algorithm, which decides the configuration of DRFM and the assignment of operations into islands with the focus on optimizing global connections; (ii) a data-forwarding scheduling algorithm, which takes advantage of the operation slacks to handle the read-port restriction of register files. On the Xilinx Virtex4 FPGA platform, experimental results with a set of real-life test cases show a 50% logic area reduction achieved by applying our approach, with a 14.6% performance improvement, compared to the traditional discrete-register-based approach. Also, experiments on small-size designs show that our algorithm produces the same number of total connections and at most one more maximum feeding-in connection compared to optimal solutions generated by ILP.

Circuits form‐valued classical, reversible and quantum optical computing with application to regular logic design

PurposeThe purpose of this paper is to introduce an approach form‐valued classical and non‐classical (reversible and quantum) optical computing. The developed approach utilizes new multiplexer‐based optical devices and circuits within switch logic to perform the required optical computing. The implementation of the new optical devices and circuits in the optical regular logic synthesis using new lattice and systolic architectures is introduced, and the extensions to quantum optical computing are also presented.Design/methodology/approachThe new linear optical circuits and systems utilize coherent light beams to perform the functionality of the basic logic multiplexer. The 2‐to‐1 multiplexer is a basic building block in switch logic, where in switch logic a logic circuit is implemented as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less‐costly in synthesizing wide variety of logic circuits and systems. The extensions to quantum optical computing using photon spins and the collision of Manakov solitons are also presented.FindingsNew circuits for the optical realizations ofm‐valued classical and reversible logic functions are introduced. Optical computing extensions to linear quantum computing using photon spins and nonlinear quantum computing using Manakov solitons are also presented. Three new multiplexer‐based linear optical devices are introduced that utilize the properties of frequency, polarization and incident angle that are associated with any light‐matter interaction. The hierarchical implementation of the new optical primitives is used to synthesize regular optical reversible circuits such as them‐valued regular optical reversible lattice and systolic circuits. The concept of parallel optical processing of an array of input laser beams using the new multiplexer‐based optical devices is also introduced. The design of regular quantum optical systems using regular quantum lattice and systolic circuits is introduced. New graph‐based quantum optical representations using various types of quantum decision trees are also presented to efficiently represent quantum optical circuits and systems.Originality/valueThe introduced methods for classical and non‐classical (reversible and quantum) optical regular circuits and systems are new and interesting for the design of several future technologies that require optimal design specifications such as super‐high speed, minimum power consumption and minimum size such as in quantum computing and nanotechnology.

Single-switch dual output flyback DC/DC converter with time multiplexing control

Controlling two outputs with a single controlling switch in the power converter presents difficulties when two contrasting actions are required to raise one output and decrease the other. This paper studies the application of time multiplexing control (TMC) technique on power converters, with particular interest on single-switch multiple-output converters. Each output has its own feedback control circuit but these discrete feedback control loops are intermittently switched to regulate the duration of the 'on period' and 'off period' of the power switches. The inclusion of multiplexing logic to incorporate multiple controllers will improve the regulation of the auxiliary outputs and the main output within the tolerances required for electronic equipment. The output errors can be distributed between the outputs according to the time sharing factor of the time multiplexing logic controller. Simulation and experimental results on a single-switch dual-output flyback converter with and without TMC are reported to verify the error sharing capability of the proposed method. This control approach suggests a possible solution in improving the overall performance of the power supply in terms of output voltage regulation.

Novel radio resource allocation strategy for multimedia content delivery over satellite multicast/broadcast systems

The provisioning of multimedia applications requires wireless networks to optimally allocate radio resource and efficiently adapt to dynamically changing wireless environment. Radio Resource Allocation (RRA) strategy is an important issue in the design of the Satellite Digital Multimedia Broadcasting (SDMB) system, aiming at providing more efficient and cost-effective delivery of broadcast/multicast (BC/MC) services to a wide range of audience. Based on the single-level channel multiplexing framework, the existing RRA strategy only performs transport channel multiplexing and assumes one-to-one ideal mapping between logical and transport channels. However, the bit rates of the logical channels do not always exactly match those of the transport channels, and this leads to inefficient usage of radio resource. To solve this problem, in this paper, a novel RRA strategy, which is capable of optimally performing both logical and transport channel multiplexing, is proposed for the SDMB system. In order to improve the resource utilisation and reduce the power consumption, two new algorithms, namely Optimum Estimation Algorithm (OEA) and Power-Oriented Adaptation (POA) algorithm, are developed to optimize the proposed 2-level channel multiplexing scheme. In comparison with the existing single-level channel multiplexing scheme, simulation results show that the proposed 2-level channel multiplexing scheme achieves significantly better performance in terms of transport/physical channel utilisation, transmission power consumption as well as total transmission capacity.

Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics

This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases.

Multiplexing ATE channels for production testing at 2.5 Gbps

We describe two versions of a multiplexing test system for multigigahertz devices. Our approach leverages test resources available in existing ATE, and achieves higher rates with added multiplexing logic. In the prototype, 32 high-speed differential-pair signals each support data at 2 Gbps to 2.5 Gbps. An updated system uses water cooling to better maintain the test electronics temperature. This system also has improved relays for better signal integrity, and better embedded calibration circuits to obtain stable operation at 2.5 Gbps. The production version is scalable to as many as 144 high-speed differential-pair signals. Integral to the design are embedded circuits that support automated, accurate timing calibration with 10-ps resolution.

Compact multiple-valued multiplexers using negative differential resistance devices

Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTD's) and heterojunction bipolar transistors (HBT's) with the folded I-V characteristic (NDR characteristic) of the RTD's providing the compact logic implementation and the HBT's providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHET's) and resonant tunneling bipolar transistors (RTBT's) is also demonstrated.

Optoelectronic differential multiplexer logic based on phototransistors/LEDs and its use in optical systems

Differential and single-ended operation are compared for optoelectronic logic based on phototransistors and LEDs. This demonstrates the advantages of operating differentially to obtain tolerant elements which do not require tuning. Fan-out levels and interconnection strategies for this logic are discussed leading to the adoption of local interconnections with a fan-out of four to support regular 2D logic arrays of 4-to-1 multiplexers. It is shown that 4-to-1 multiplexers not only minimise the number of elements required to perform a function but also minimise the number of interstage connections and the number of stages required. The flexibility and power of the logic functionality and interconnection approach are demonstrated for both combinatorial and sequential logic where the use of shared outputs leads to significant logic compaction. This considerably increases the functionality and parallelism offered by a system.

Multiplexing issues in communication system design

This paper considers some of the multiplexing issues in communication system design by examining overall system issues. In particular, we distinguish physical multiplexing of resources from logical multiplexing of streams. Both physical-resource multiplexing and logical multiplexing determine the service that can be provided by a communication system. We also discuss two issues affected by logical multiplexing - flow control and the relationship between control and data streams of a connection. We conclude that the granularity of physical resource sharing must be fine enough to meet the jitter and latency constraints of demanding applications. Also, high speed communication systems should restrict their logical multiplexing to layer 3.

Wavelength-discriminating photodetector for lightwave systems

We demonstrate that a dual-wavelength photodetector can be used to determine simultaneously the wavelength and the power level of a lightwave signal. The signal wavelength is determined by monitoring the ratio of the two outputs from this photodetector at the crossover of its responsivity curves; the signal level is determined from the sum of the two outputs. Possible applications for this type of photodetector include mode-control of single-frequency injection lasers, direct demodulation for lightwave systems utilising frequency-shift-keyed transmission, wavelength-division multiplexing and optical logic.

An algorithm for designing multiplexer logic circuits

Several algorithms arc now available for designing combinational logic circuits using multiplexers. In the present paper, the authors propose an algorithm which loads to a design, in a simple way, to meet one of two objectives discussed in the paper. The authors feel that the algorithm is simpler than some of the existing methods involving similar objectives.

Traffic control systems hardware

In the past ten years the technology of traffic control has experienced extensive change. Equipment which was once familiar to traffic engineers and maintenance personnel has been supplanted by the new breed of devices using solid-state digital circuitry, sophisticated multiplexing, and microprocessor logic. The changes in operational capability and technical performance of systems brought about by these advances have been widely acknowledged. However, the impact upon the user is only beginning to be realized, as traffic engineers learn to cope with such considerations as operator training, maintenance, reliability, updating, and expansion. The current developments in traffic control systems hardware and the experience that is starting to be collected with respect to their installation and use are discussed. Technical and nontechnical factors are discussed and future directions are predicted.