Reconfigurable Operators: New Configuration Logic Blocks for Novel FPGA

Abstract

For current FPGA architectures, the flne-grain programmable blocks are the most ∞exible ones. However, they bring in massive conflguration bits-stream and much performance loss. In this paper, we propose new conflguration logic blocks for the latest FPGA, a collection of Reconflgurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a speciflc function set. Considering the ∞exibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Speciflc Integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use conflguration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on conflguration bits-stream and comparable delay compared with Virtex5 FPGA.