High speed low power multiple bit subtracter circuit design using high performance domino logic

Abstract

The domino logic style is very attractive for designing high performance digital logic circuits in Very Large Scale Integrated microprocessor chips. In this paper a four bit subtractor circuit is designed using different domino logic styles and its performance is compared with one another. The simulations were performed using L=0.12μm technology along with a supply voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.2V. The simulation results show that the delay of the subtractor circuit is very low compared to the conventional four bit subtractors. The delay is in the order of Pico seconds. These new multiple bit subtractors show improved noise immunity low leakage and low power consumption without much speed penalty. In this paper the performance of multiple bit subtractors designed using high speed domino technique, conditional keeper technique and leakage current mirror technique is analyzed in detail. Also the layout level simulations were performed to study the performance of multiple bit subtractor circuits.