Stability enhancement techniques for nanoscale SRAM circuits: A comparison

Abstract

Four circuit techniques for high data stability and low leakage power consumption in static CMOS memory circuits are compared in this paper. The techniques that provide the highest data stability, the lowest leakage power consumption, and the smallest memory cell area are identified. The first circuit technique employs a dynamic voltage swing wordline driver to control the operation of the standard six-transistor (6 T) memory cells. The wordline voltage swing is dynamically tuned during read and write operations in order to simultaneously enhance the read stability and the write margin without increasing the size of the transistors in the SRAM cell. The other three circuit techniques tackle the data stability challenge by modifying the memory cell circuit structure. A nine-transistor (9 T), an eighttransistor (8 T), and a dual-threshold-voltage (dual-Vt) seven-transistor (7 T) SRAM circuit are considered in this paper. The data storage nodes are isolated from the bitlines with these techniques, thereby significantly enhancing the read stability as compared to the standard 6 T SRAM circuits. Among the evaluated memory circuits, the 9 T and the 8 T SRAM cells provide the highest data stability during a read operation. The read stability of the 9 T and the 8 T SRAM cells is 80% higher as compared to a standard 6T SRAM cell sized for data stability (with beta = 3) in a 65 nm CMOS technology. Alternatively, the dynamic wordline voltage swing technique offers the smallest area and the dual-Vt 7 T SRAM cell consumes the lowest leakage power among the evaluated memory cells.