Low Power Area Efficient Multiplier Using Shannon Based Multiplexing Logic

Abstract

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The median filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the pixels. Sorting in turn consists of comparator which includes adders and multiplier. Multiplication is a fundamental operation in arithmetic computing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the multiplier circuits. The Carry Save Array (CSA) multiplier is designed by using the proposed adder cell based on multiplexing logic. The proposed adder circuit is designed by using Shannon theorem.The multiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based multiplier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based multiplier circuits are simulated by using 90nm feature size and with various supply voltages. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.