Low power high speed 1-bit full adder circuit design at 45nm CMOS technology

Abstract

One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of improvement has been done in this area to refine the architecture and performance of full adder circuit design. In this paper two designs of novel 1-bit full adder cell at 45nm CMOS technology is implemented by using ten transistors (10-T) along with the three existing 1-bit full adder cell. Later the complete comparison and verification is performed with the different existing and proposed adder cells on different supply voltages at 100MHz operating frequency. From the simulation results by performing the comparison among proposed adder cells and existing adder cells it is found that the proposed adder cells are better than the existing adder cells in terms of power consumption, delay and power delay product (PDP). From the simulation result it is observed that the first proposed adder circuit using XOR module has achieved maximum saving of power 91.65%, saving of delay 59.37% and saving of overall PDP of 91.64% when compared to existing Static Energy Recovery Full (SERF) full adder and Gate Diffusion Input (GDI) full adder circuit respectively. When second proposed adder circuit using XOR module is compared with existing SERF and GDI adder circuit maximum saving of power 93.04%, saving of delay 76.76% and saving of overall PDP of 96.01% is achieved. All above statistical analysis is given by performing the comparison between existing and proposed adder circuits which have same number of transistors count (10-T) in designing at supply voltage 1 volt.