Low voltage, high speed FinFET based 1-bit BBL-PT full adders

Abstract

Feature size of CMOS technology continues to scale down; new devices like FinFET are experimented and proposed as an alternative device due to its superior characteristics. In this paper we have presented low voltage, high speed 1-bit full adder cells in Branch Based Logic and Pass Transistor (BBL-PT) logic by using FinFET model parameters. In BBL-PT full adder lies a drawback i.e. voltage step existed in sum output. That could be eliminated in the proposed logics by using the diode connected FinFET (D-FinFET) inverter, N-type FinFET inverter and modified current sink restorer structures. Proposed full adder circuits are compared with conventional adder circuits, and proposed circuits have demonstrated the good delay performance. The performance of proposed and other conventional full adder circuits are examined using Cadence and the model parameters of 180 nm CMOS technology with +1.2 V supply rail voltage and 20 nm FinFET model files with +0.6 V supply rail voltage with frequency 100 MHz.