High performance and energy efficient FinFET based 1-bit PT full adders

Abstract

This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be eliminated in proposed circuits by using diode connected FinFET restorer (D-FinFETs) and buffer as a restorer structures. The proposed circuits are simulated and verified in Cadence software 20 nm FinFET compact model files with +0.6 V supply rail with frequency 0.05 GHz. The delay of D-FinFET and buffer as restorer structure are 62 ns and 75 ns respectively, and power consumption of these structures are 152 μW and 14.2 μW respectively. It is observed that proposed circuits are exhibiting improved delay and power performance.