Multiple Transistors Research Articles

Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and Vdd with a high voltage gain of ∼29 and a sharp transition of 0.28 V at Vdd = 3 V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for Vdd = 3 V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

20 $\mu$A to 100 mA DC–DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS

A DC-DC buck converter capable of handling loads from 20 μA to 100 mA and operating off a 2.8-4.2 V battery is implemented in a 45 nm CMOS process. In order to handle high battery voltages in this deeply scaled technology, multiple transistors are stacked in the power train. Switched-Capacitor DC-DC converters are used for internal rail generation for stacking and supplies for control circuits. An I-C DAC pulse width modulator with sleep mode control is proposed which is both area and power-efficient as compared with previously published pulse width modulator schemes. Both pulse frequency modulation (PFM) and pulse width modulation (PWM) modes of control are employed for the wide load range. The converter achieves a peak efficiency of 75% at 20 μA, 87.4% at 12 mA in PFM, and 87.2% at 53 mA in PWM.

A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS

A wideband frequency multiplier that effectively generates and combines the even harmonics from multiple transistors is proposed. It takes advantage of standing-wave formation and loss cancellation in a distributed structure to generate high amplitude signals resulting in high harmonic power. Wide bandwidth operation and odd harmonic cancellation around the center frequency are the inherent properties of this frequency multiplier. Using this methodology, we implemented a frequency doubler that operates from 220 GHz to 275 GHz in a standard 65 nm CMOS process. Output power of 6.6 dBm (0.22 mW) and conversion loss of 11.4 dB are measured at 244 GHz.

Growth of high Ge content SiGe on (110) oriented Si wafers

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~20% higher, whereas for dichlorosilane based processes it is ~30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.

Power optimized variation aware dual-threshold SRAM cell design technique

Bulk complementary metal-oxide semiconductor (CMOS) technology is facing enormous challenges at channel lengths below 45 nm, such as gate tunneling, device mismatch, random dopant fluctuations, and mobility degradation. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube-based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology. In this paper, we propose a low-power variation-immune dual-threshold voltage carbon nanotube field effect transistor (CNFET)-based seven-transistor (7T) static random access memory (SRAM) cell. The proposed CNFET-based 7T SRAM cell offers ∼1.2× improvement in standby power, ∼1.3× improvement in read delay, and ∼1.1× improvement in write delay. It offers narrower spread in write access time (1.4× at optimum energy point [OEP] and 1.2× at 1 V). It features 56.3% improvement in static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE (high-performance simulation program with integrated circuit emphasis) environment.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.

Improvement on thermal stability of power heterojunction bipolar transistor using non-uniform finger spacing

One method of non-uniform finger spacing is proposed to enhance thermal stability of multiple finger power heterojunction bipolar transistor. Using coupling thermal resistance to characterize the influence of the change of emitter spacing on thermal coupling, the relation between coupling thermal resistance and emitter spacing is obtained. Temperature distribution on the emitter fingers of multi-finger heterojunction bipolar transistor is studied by a numerical electro-thermal model. The results show that the heterojunction bipolar transistor with non-uniform finger spacing has a smaller temperature difference between fingers thant the traditional uniform finger spacing heterojunction bipolar transistor under the same power dissipation. So the method of non-uniform finger spacing is very effective to enhance the thermal stability.

Reconfigurable Blocks Based on Balanced Ternary

Silicon-on-Insulator CMOS fabrication technologies are now available that offer a number of unique advantages including the availability of multiple simultaneous transistor thresholds. This paper proposes and analyzes a number of circuits for a reconfigurable array organization based on a balanced ternary logic system in which the logic set {??1, 0,?+?1} maps directly to equivalent voltage levels {?1V, 0V, +1V}. A number of low-power, high-speed components, such as a ternary buffer, flip-flop and look-up table, are described and simulated based on the characteristics of a commercially available silicon-on-sapphire process. A brief analysis indicates that the circuits will be capable of operating at the 22 nm technology node and beyond. A simple example of a Sigma-Delta Modulated FIR filter is mapped to the array and some preliminary estimates are made of its performance and area based on both 3-input and 4-input look-up tables. The simulated ternary array is shown to be capable of operating at clock speeds of more than 200 MHz such that it will readily support standard video bandwidths at useful over-sampling ratios.

Air-Stable Ambipolar Field-Effect Transistors and Complementary Logic Circuits from Solution-Processed n/p Polymer Heterojunctions

We demonstrate the use of n/p polymer/polymer heterojunctions deposited by sequential solution processing to fabricate ambipolar field-effect transistors and complementary logic circuits. Electron and hole mobilities in the transistors were ∼0.001-0.01 cm(2)/(V s) in air without encapsulation. Complementary circuits integrating multiple ambipolar transistors into NOT, NAND, and NOR gates were fabricated and shown to exhibit sharp signal switching with a high voltage gain.

Analog Operation and Harmonic Distortion Temperature Dependence of nMOS Junctionless Transistors

This paper compares the analog parameters of the multiple gate Junctionless transistors with the ones presented by classical inversion mode Trigate devices from 473 K down to 223 K. The transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both Junctionless and inverse mode devices with different fin widths. Also, the non-linearity of this novel architecture is studied in terms of the total and the third order harmonic distortions (THD and HD3, respectively) both at a fixed input voltage and at a targeted output swing. According to the study, the drain current of Junctionless transistors have exhibited lower temperature dependence with gm/IDS at moderate/strong inversions and their AV increase with the temperature, whereas the maximum AV of Trigate devices is obtained at room temperature. Junctionless also present better THD and HD3 with respect to the classical Trigate transistors.

Estimation of Heavy-Ion LET Thresholds in Advanced SOI IC Technologies From Two-Photon Absorption Laser Measurements

The laser energy thresholds for SEU for SOI 1-Mbit SRAMs built in Sandia's 0.35-μm SOI technology were measured using carrier generation by two-photon absorption. The laser measurements were correlated to heavy-ion threshold LET measurements to determine an empirical relationship between laser energy threshold and heavy-ion threshold LET. This empirical relationship was used to estimate the threshold LETs for other circuits built in Sandia's 0.35-μm SOI technology and SRAMs built in IBM's 45 and 65-nm SOI technologies. For an ASIC built in Sandia's 0.35-μm SOI technology the estimated threshold from laser measurements was close to the measured heavy-ion threshold LET. However, for a dual-port SRAM also built in Sandia's 0.35-μm SOI technology and for the 45- and 65-nm IBM SOI SRAMs, the threshold LETs estimated from laser measurements did not correlate to the measured heavy-ion threshold LETs. For the IBM SRAMs, the likely cause of the discrepancy between the threshold LETs estimated from laser measurements and the threshold LETs measured by heavy-ion testing is due to the laser pulse simultaneously injecting charge into multiple transistors within a memory cell and/or in adjacent memory cells. This is due to the relatively large size of the laser spot size compared to the size of the SEU sensitive volume of the IBM SOI devices. The hardness assurance implications of these results are discussed.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TiN) gate electrode thickness has been investigated in n- and p-channel SOI multiple gate field-effect transistors (MuGFETs) through low-frequency noise, charge pumping and static measurements as well as capacitance–voltage curves. The results suggest that a thicker TiN metal gate electrode gives rise to a higher EOT, a lower mobility and a higher interface trap density. The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TiN metal gate thickness and at higher V GF . In addition, it is demonstrated that post-deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TiN gate electrode thickness, where a continuous variation of EOT and an increase on the degradation of the interface quality are observed.

Correlating the Nanostructure and Electronic Properties of InAs Nanowires

The electronic properties and nanostructure of InAs nanowires are correlated by creating multiple field effect transistors (FETs) on nanowires grown to have low and high defect density segments. 4.2 K carrier mobilities are approximately 4x larger in the nominally defect free segments of the wire. We also find that dark field optical intensity is correlated with the mobility, suggesting a simple route for selecting wires with a low defect density. At low temperatures, FETs fabricated on high defect density segments of InAs nanowires showed transport properties consistent with single electron charging, even on devices with low resistance ohmic contacts. The charging energies obtained suggest quantum dot formation at defects in the wires. These results reinforce the importance of controlling the defect density in order to produce high quality electrical and optical devices using InAs nanowires.

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S11 of the RF front-end is lower than −11.4 dB over the whole band of 200 kHz–2 GHz. The variable gain range is 12–42 dB at 0.25 GHz and 4–36 dB at 2 GHz. The DSB NF at maximum gain is 3.1–6.1 dB. The IIP3 at middle gain is −4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.

Enhanced Plasma Wave Detection of Terahertz Radiation Using Multiple High Electron-Mobility Transistors Connected in Series

We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> W/Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sup> . The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel.

Liquid Cooled Cold Plates for Industrial High-Power Electronic Devices—Thermal Design and Manufacturing Considerations

Electronics cooling research has been largely focused on high heat flux removal from computer chips in the recent years. However, the equally important field of high-power electronic devices has been experiencing a major paradigm shift from air cooling to liquid cooling over the last decade. For example, multiple 250-W insulated-gate bipolar transistors used in a power drive for a 7000-HP motor used in pumping or in locomotive traction devices would not be sufficiently cooled with air-cooling techniques. Another example is a “hockey puck” SCR of 63 mm diameter used to drive an electric motor that could dissipate over 1500 W and is difficult to cool with air because of the shape of the device. Other devices include radio-frequency generators, industrial battery chargers, printing press thermal and humidity control equipment, traction devices, mining devices, crude oil extraction equipment, magnetic resonance imaging, and railroad engines. This article classifies the cold plates into four types: formed tube cold plate, deep drilled cold plate, machined channel cold plate, and pocketed folded-fin cold plate. The article further discusses selection of cold plate type and channel configuration, and some of the relevant manufacturing issues. It is recommended that the thermal designer be involved in the early stages during the electrical design and layout of the devices.

Ultrathin Body Effects in Multiple Gate SOI Transistors

We will review the electrostatics and transport properties of charge carriers in ultrathin multiple gate SOI transistors. Both electron and hole inversion layers will be studied and characterized as a function on the silicon thickness and for different crystallographic orientations.

Real-time vapour sensing using an OFET-based electronic nose and genetic programming

Electronic noses (e-noses) are increasingly being used as vapour sensors in a range of application areas. E-noses made up of arrays of organic field-effect transistors (OFETs) are particularly valuable due the range and diversity of the information which they provide concerning analyte binding. This study demonstrates that arrays of OFETs, when combined with a data analysis technique using Genetic Programming (GP), can selectively detect airborne analytes in real time. The use of multiple parameters – on resistance, off current and mobility – collected from multiple transistors coated with different semiconducting polymers gives dramatic improvements in the sensitivity (true positive rate), specificity (true negative rate) and speed of sensing. Computer-controlled data collection allows the identification of analytes in real-time, with a time-lag between exposure and detection of the order of 4 s.

Alternating patterns on single-walled carbon nanotubes

Scientific and technological interest in one-dimensional nanomaterials, in particular carbon nanotubes, is a result of their fascinating properties and their ability to serve as templates for directed assembly. For applications in nanoelectronics it is necessary to create ordered arrays of nanotubes for large-scale integrated circuits, an area in which there has been significant progress, and to produce controllable patterns on individual nanotubes so that multiple transistors can be fabricated on them, an area where progress has been slower. Here, we show that judiciously selected crystalline block copolymers can be periodically decorated along carbon nanotubes, leading to amphiphilic, alternating patterns with a period of approximately 12 nm. In addition, end-functionalization of the block copolymers allowed gold nanoparticles to be periodically attached to the nanotubes. This approach provides a facile technique for the periodic patterning of one-dimensional nanomaterials.