Multiple Cell Upsets Research Articles

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction

Static random access memories (SRAMs) are key in electronic systems. They are used not only as standalone devices, but also embedded in application specific integrated circuits. One key challenge for memories is their susceptibility to radiation-induced soft errors that change the value of memory cells. Error correction codes (ECCs) are commonly used to ensure correct data despite soft errors effects in semiconductor memories. Single error correction/double error detection (SEC-DED) codes have been traditionally the preferred choice for data protection in SRAMs. During the last decade, the percentage of errors that affect more than one memory cell has increased substantially, mainly due to multiple cell upsets (MCUs) caused by radiation. The bits affected by these errors are physically close. To mitigate their effects, ECCs that correct single errors and double adjacent errors have been proposed. These codes, known as single error correction/double adjacent error correction (SEC-DAEC), require the same number of parity bits as traditional SEC-DED codes and a moderate increase in the decoder complexity. However, MCUs are not limited to double adjacent errors, because they affect more bits as technology scales. In this brief, new codes that can correct triple adjacent errors and 3-bit burst errors are presented. They have been implemented using a 45-nm library and compared with previous proposals, showing that our codes have better error protection with a moderate overhead and low redundancy.

Reliability of Memory Storage System UsingDecimal Matrix Code and Meta-Cure

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used. The soft error rate in memory cells Multiple Cell Upset (MCU) are rapidly increasing. MCU have become a serious reliability issue in the memory. A novel Decimal Matrix Code (DMC) based on divide- symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. The Encoder-Reuse Technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be a part of the decoder. The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibiterrors.Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failure.

Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes

To avoid data corruption, error correction codes (ECCs) are widely used to protect memories. ECCs introduce a delay penalty in accessing the data as encoding or decoding has to be performed. This limits the use of ECCs in high-speed memories. This has led to the use of simple codes such as single error correction double error detection (SEC-DED) codes. However, as technology scales multiple cell upsets (MCUs) become more common and limit the use of SEC-DED codes unless they are combined with interleaving. A similar issue occurs in some types of memories like DRAM that are typically grouped in modules composed of several devices. In those modules, the protection against a device failure rather than isolated bit errors is also desirable. In those cases, one option is to use more advanced ECCs that can correct multiple bit errors. The main challenge is that those codes should minimize the delay and area penalty. Among the codes that have been considered for memory protection are Reed-Solomon (RS) codes. These codes are based on non-binary symbols and therefore can correct multiple bit errors. In this paper, single symbol error correction codes based on Reed-Solomon codes that can be implemented with low delay are proposed and evaluated. The results show that they can be implemented with a substantially lower delay than traditional single error correction RS codes.

Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs

We experimentally characterized and compared the soft error rates of 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs by conducting accelerated alpha and neutron irradiation tests. Measurement results show that an SOTB SRAM has better soft error immunity than a bulk SRAM. In particular, the number of 2-bit multiple cell upsets (MCUs) of SOTB SRAM was smaller by two orders of magnitude than that of bulk SRAM, and the number of 3-bit or larger MCUs decreased further. In addition, the reverse body bias (RBB) reduced the soft error rate of SOTB SRAM to two-thirds of zero body bias (ZBB). To investigate this dependence on body bias, we evaluated the sensitive cross sectional area for ZBB and RBB with 3D technology computer aided design device simulations. The simulation results show that the RBB decreases the sensitive cross-sectional area of an SOTB device for small linear energy transfer (LET) ions, which is consistent with the measured dependence on body bias.

Angular dependence of proton single event multiple-cell upsets in nanometer SRAM

Single event multiple-cell upsets (MCU) increase sharply as the feature size of semiconductor devices shrinks. MCU poses a large challenge on present radiation hardening technology and modeling test technique. Experimental study of the influence of proton incidence angle on single event multiple-cell upsets in 90 nm static random access memory (SRAM) for middle and high energy proton is carried out. The result shows that MCU percentage and multiplicity increase with increasing proton energy, and the MCU topological pattern presents a certain track-orientation characteristic along the trajectories of the incidence ion when the incidence proton is tilted along the X-direction or Y-direction. Single event upset (SEU) cross section has no evident angular dependence. There is some difference in proton MCU cross section between normal incidence and tilt angle incidence only for 30 MeV proton. Angular effect of proton MCU is associated with proton energy. Due to the lower efficiency of Monte-Carlo method in calculating proton MCU, a fast calculation method for cross section, which aims at single event MCU induced by proton nuclear reaction, is adopted. The binary cascade model in Geant4 toolkit serves as event generators in middle on high proton nuclear reaction. In terms of double differential scattering cross section of secondary particle from proton-material spallation reaction, proton MCU cross section is calculated through integration over the entire space of memory cells array. Based on the distribution of secondary particles, those spallation products with the highest linear energy transfer (LET) and longest range are revealed to emit preferentially in the forward direction, which is the root cause why the angular effect of proton-induced MCU exists. The angular dependence of single event MCU in nanometer SRAM depends strongly on proton energy and critical charge. The higher the proton energy is, the wider the angular distribution of secondary particle is, the greater the energy and LET value of the lateral scattered secondary particle is; and so the angular enhancement effect in MCU cross section for lower energy protons is greater than the higher energy protons. MCU cross section is more isotropic with the increase of the proton energy. Angular effect in MCU cross section becomes stronger with the increase of the critical charge for the same energy proton.

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets

We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.

Statistics and methodology of multiple cell upset characterization under heavy ion irradiation

Mean and partial cross-section concepts and their connections to multiplicity and statistics of multiple cell upsets (MCUs) in highly-scaled digital memories are introduced and discussed. The important role of the experimental determination of the upset statistics is emphasized. It was found that MCU may lead to quasi-linear dependence of cross-sections on linear energy transfer (LET). A new form of function for interpolation of mean cross-section dependences on LET has been proposed.

English

Protection codes are necessary to shield memory cells, to maintain good quality level of reliability. But, we don’t find any optimized error detection and correction methods. Therefore, in this paper, we present a high performance Decimal Matrix Code to assure the reliability of memory. This protection code utilizes decimal procedure to detect errors, so that more errors were detected and corrected up to 32. Transient multiple cell upsets (MCUs) are major problems in the reliability of memories exposed to radiation environment. To prevent cell upsets from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but they would require higher delay so an efficient ERT (encoder-reuse technique) is proposed to reduce the area overhead of extra circuits, it utilize DMC encoder itself to be part of the decoder.

Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance

This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.

A Method to Design SEC-DED-DAEC Codes With Optimized Decoding

Single error correction-double error detection- double adjacent error correction (SEC-DED-DAEC) codes have been proposed to protect SRAM devices from multiple cell upsets (MCUs). The correction of double adjacent errors ensures that the most common types of MCUs are corrected. At the same time, SEC-DED-DAEC codes require the same number of parity check bits as traditional SEC-DED codes. The main overhead associated with SEC-DED-DAEC codes is the increase in decoding complexity that can impact access time and circuit power and area. In this paper, a method to design SEC-DED-DAEC codes with optimized decoding is presented and evaluated. The proposed scheme starts by setting some constraints on the parity check matrix of the codes. Those constraints are then used to simplify the decoding. The proposed scheme has been implemented and evaluated for different word-lengths. The results show that, for data words of 32 bits, the scheme can be implemented with the same number of parity check bits as SEC-DED codes. For 16 and 64 bits words, an additional parity check bit is required, making the scheme less attractive. With the proposed method, the decoders can be optimized for area or speed. Both implementations are evaluated and compared with existing SEC-DED-DAEC decoders. The results show that the proposed decoders reduce significantly the circuit area, power, and delay. Index Terms—SEC-DAEC codes, Multiple Cell Upsets (MCUs), error correction codes, SRAM memories.

English

The proposed security code utilizes decimal method to detect errors, so that more errors were detected and corrected. At the present days to maintain good level of reliability, it is required to protect memory cells using protection codes, for this purpose, various error detection and correction methods are being used. In the paper 64-bit Decimal Matrix Code was proposed to assure the dependability of memory. Here to detect and correct up to 50% errors. The results showed that the proposed scheme has a protection level against large MCUs in memory. To avoid MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would need higher delay overhead. Previously, matrix codes (MCs) based on Hamming codes include been proposed for memory safety. The main problem is that they are double error correction codes and the error correction capabilities are not enhanced in each case. Transient multiple cell upsets (MCUs) are appropriate major problems in the reliability of memories exposed to energy environment. In the new method we are implement 64-bit decimal matrix for error correction in memories. In the new method to increase the error correction rate compared to the 32-bit decimal matrix code. Moreover, the ERT (encoder-reuse technique) is proposed to decrease the area transparency of extra circuits exclusive of disturbing the total encoding and decoding processes. ERT (encoder re use technique) use DMC encoder itself to be part of in the decoder.

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

Multiple Cell Upset Classification<newline/> in Commercial SRAMs

While single bit upsets on memories and storage elements are mitigated with either the use of redundancy and/or error correction codes, Multiple-Cell-Upsets (MCU) may become a significant threat to the integrity of systems when the corrupted cells belong to the same word. In this paper, we identify four types of MCUs as they were recorded during several irradiations under an atmospheric-like neutron beam (ISIS facility). An analysis is done on the underlying reasons of occurrence of each MCU type, as well as their shapes and sizes in order to classify them. The results of this work concern a commercial 90 nm SRAM that was tested under an atmospheric neutron beam in static and dynamic mode. It is shown that, when the memory is in dynamic mode, not only the typical MCUs that involve a few flipped cells may appear but also large clusters of upsets are possible to occur with hundreds or even thousands of cells being affected.

Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process

Technology scaling increases the role of charge sharing and bipolar effect with respect to multiple cell upset. We analyze the contributions of cell distance and well-contact density to suppress MCU by device-level simulations and neutron experiments. Device simulation results reveal that the ratio of MCU to SEU exponentially decreases by increasing the distance between redundant latches. MCU is suppressed when well con- tacts are placed between redundant latches. Experimental results also show that the ratio of MCU to SEU exponentially decreases by increasing the distance between cells. MCU is suppressed effectively by increasing the density of well contacts.

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

This paper presents measurement results of alpha-particle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.

Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement

Radiation particles can impact registers or memories creating soft errors. These errors can modify more than one bit causing a multiple cell upset (MCU) which consists of errors in registers or memory cells that are physically close. These MCUs can affect a single word, producing adjacent bit errors. Hamming codes are commonly used to protect memories or registers from soft errors. However, when multiple errors occur, a Hamming code may not detect them. In this letter, single-error-correction double adjacent error detection Hamming codes are presented for 16-, 32-, and 64-bit words. Additionally, single-error-correction double-error-detection triple adjacent error detection codes based on extended Hamming are presented as well. The enhanced detection is achieved by performing a selective shortening and reordering of the Hamming matrix so adjacent errors result in a syndrome that does not match that of any single error. These codes will help in the detection of MCUs in SRAM memory designs.

Effect of topological placement of memory cells in memory chips on multiplicity of cell upsets from heavy charged particles

An analysis of factors influencing operational reliability of memory chips has been performed. Different topological configurations of 6-transistors memory cells have been considered. Two configurations of cells most sensitive to the influence of multiple cell upsets (MCUs) have been identified.

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the existing Hamming, MCs, and punctured difference set (PDS) codes. The obtained results show that the mean time to failure (MTTF) of the proposed scheme is 452.9%, 154.6%, and 122.6% of Hamming, MC, and PDS, respectively. At the same time, the delay overhead of the proposed scheme is 73.1%, 69.0%, and 26.2% of Hamming, MC, and PDS, respectively. The only drawback to the proposed scheme is that it requires more redundant bits for memory protection.

Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations

This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CADENCE tool). The method is validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separate-well designs). These methodologies have been validated in the case of 1000 inverters chain and for heavy ions and demonstrate the impact of the quenching effect. Furthermore, both the designs were considered and the analyses are consistent with experiments and this allows for identification of the quenching effect as the main mechanism responsible for the difference in SET sensitivity. However, the modeling approach can be also used for other logical cells or/and complex radiation environments, to determine SET cross sections, SET cartographies and SET characteristics. This method is applied to SEU analyses, i.e., SBU (Single Bit Upset) and MCU (Multiple Cell Upset) for 65-nm bulk SRAM memory and neutron/proton SET modeling.

At-Speed SEE Testing of RHBD Embedded SRAMs

We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell Upsets (MCU), Multiple Bit Upsets (MBU), persistent errors and transient errors. Error Detection and Correction (EDAC) can reduce the residual error rate due to SEU by multiple orders of magnitude. Consequently, careful testing of the at-speed test structure is essential to detect and quantify the risk of rare, uncorrectable MBU.