Multiple Cell Upsets Research Articles

Heavy ion energy influence on multiple-cell upsets in small sensitive volumes: from standard to high energies

Heavy ion energy influence on multiple-cell upsets in small sensitive volumes: from standard to high energies

Heavy Ion Energy Deposition and SEE Intercomparison Within the RADNEXT Irradiation Facility Network

RADNEXT is an EU-funded network of irradiation facilities and radiation effects experts aimed at increasing the quantity and quality of user access to accelerator infrastructure, and improving the diversity and harmonization across facilities. Along with the beam provision to worldwide radiation effects users, RADNEXT has an ambitious research program oriented at improving radiation effects testing, of which an example of a heavy ion facility inter-comparison at very different energy regimes is included in this work. In particular, energy deposition distributions in a silicon solid-state detector and the Single Event Upset (SEU) and Multiple Cell Upset (MCU) behaviour are compared amongst heavy ion beams of similar LET, but very different energies (i.e., from the more classical ~10 MeV/u regime up to several hundreds of MeV/u).

Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau

Based on the Yangbajing International Cosmic Ray Observatory in Lhasa with an altitude of 4300 m, a long-term real-time experiment is carried out in order to measure the atmospheric radiation induced soft errors in 14 nm FinFET and 28 nm planar CMOS SRAM array. The underlying mechanisms are also revealed. Five boards are used in the test, four of which are equipped with 28-nm process devices, and one board is equipped with 14-nm process devices. After removing the unstable bad bits, the actual effective test capacity is 7.1 Gb. During the test, the on-board FPGA reads the stored contents of all the tested devices in real time, reports the error information (occurrence time, board number, column number, device number, error address, error data) and corrects the error. The duration of the test is 6651 h. A total of 56 single event upset (SEU) events are observed, they being 24 single bit upset (SBU) events and 32 Multiple Cell Upset (MCU) events. Based on previous results of 65-nm SRAM, the study finds that SER continues to decrease with the reduction of process size, but the proportion of MCU in 28-nm process devices (57%) exceeds SBU, which is a process “maximum point” of MCU sensitivity, and the maximum size of MCU is 16 bits. Although the Fin spacing of the 14-nm FinFET device is only about 35 nm, and the critical charge decreases to sub-fC, the introduction of the FinFET structure leads to the change of charge collection and the sensitive volume sharing mechanism , and the shallow trench isolation leads to the narrowing of the charge diffusion channel. On the other hand, the surface area of the sensitive volume decreases to 0.0024 μm<sup>2</sup>, resulting in a significant decrease in the soft error rate of both SBU and MCU in the 14-nm process.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of <i>n</i> rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

Construction Technique and Evaluation of High Performance t-bit Burst Error Correcting Codes for Protecting MCUs

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance [Formula: see text]-bit Burst Error Correcting (BEC) codes. Parity check matrices ([Formula: see text]) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting [Formula: see text]-bit burst errors caused by MCUs.

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application

Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the reliability of static random access memories (SRAMs) in space application. Due to radiation, single cell or multiple cells of a memory are corrupted. The chances of errors in more than one memory cells are also increasing due to continuous down scaling of technology. Single error, double or triple adjacent errors are most common in this case. Several error correction codes are already introduced for protecting the memories. But many existing error correcting codes have either higher delay and/or power consumption and/or decoder error rate. In this paper, we have introduced 16-bit, 32-bit and 64-bit information length, uniquely decodable single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes with lower power consumption and delay. In our design, same H-matrix is used for implementing both SEC-DAEC and SEC-DAEC-TAEC codes. Both FPGA and ASIC based synthesis results show that proposed SEC-DAEC and SEC-DAEC-TAEC codes with dimensions (24, 16), (41, 32) and (75, 64) are better compared to existing same dimension codes with respect to area, power and delay. Since, the proposed SEC-DAEC and SEC-DAEC-TAEC codes have low encoder and decoder delay which corresponds to low writing and reading time, consume significantly low power and have zero decoder error rate, so proposed codec can be used for memories in space application.

Mechanism and Equivalence of Single Event Effects Induced by 14 MeV Neutrons in High-Speed QDR SRAM

Single-bit upset (SBU) and multiple-cell upset (MCU) features of high-speed QDR-SRAM are revealed under the 14 MeV neutron irradiation. By comparing with the high-altitude real atmosphere test results directly, the equivalence of 14 MeV neutrons for atmospheric neutron-induced single event effect (SEE) evaluation is investigated. It is found that, compared with the 65 nm planar device, the SBU cross-section of 14 nm FinFET SRAM decreases to 1/58 and the proportion of MCU shows little difference, which results from the narrow channel between fin and substrate caused by shallow channel isolation in 14 nm FinFET process, and the charge sharing effect between fins is weakened. The SBU and MCU cross-sections under the 14 MeV neutron irradiation are underestimated by 22.8% and 85.7%, respectively. Besides, the probability and maximum size of MCU are both smaller than those in the real atmosphere. The MCU shape tends to be vertical, resulting from the smaller vertical spacing of sensitive volumes (about 100 nm). Further Monte-Carlo simulation shows that the total yield of secondary ions produced by atmospheric neutrons is higher than that produced by 14 MeV neutrons. Major Components of the “useful” products are p, Si, α, etc., which are the main cause of SBU events. Besides, compared with 14 MeV neutrons, atmospheric neutrons generate more kinds of secondary ions in the SV within the scope from p to W, and the diverse high-Z elements, such as W, Ta, Hf, etc., are the main cause of MCU events. Moreover, the maximum LET of secondary ions can reach 31.5 MeV·cm2/mg. The equivalence of using 14 MeV neutrons for atmospheric neutron-induced SEE evaluation is closely related to the critical charge of the device under test.

Characteristic Charge Collection Mechanism Observed in FinFET SRAM Cells

This article investigates the single-event effects on 16-nm bulk field-effect transistors (FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation. These upsets are analyzed and classified according to voltage, linear energy transfer of ions, data patterns, and fail bit patterns. The analysis suggested a characteristic charge collection mechanism attributable to the FinFET structure. Estimation of a unique sensitive area shape based on cross sections is also discussed.

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the “worst direction” corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7–4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte–Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

Characterization of Single-Event Upsets Induced by High-LET Heavy Ions in 16-nm Bulk FinFET SRAMs

For advanced technology nodes, the static random-access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for FinFET inhibits the charge collection compared to the planar transistor structure. In this work, heavy ion tests were conducted for 16 nm bulk FinFET dual-port SRAM at two high linear energy transfers (LETs) of 60 MeV∙cm2/mg and 85 MeV∙cm2/mg. The non-saturating behavior of the SEU cross-sections and event cross-sections for a bit cell is observed even over the LET of 60 MeV∙cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show the Single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high energy particles. The parasitic bipolar effect is also serious for 16nm FinFET SRAM as former planar SRAM, but the charge sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this paper will help designers estimate the Error Correcting Code (ECC) and interleaving design parameters for radiation hardened SRAM designs at the 16 nm FinFET process.

Real-Time Characterization of Neutron-Induced SEUs in Fusion Experiments at WEST Tokamak During D-D Plasma Operation

We conducted a real-time soft-error rate characterization of CMOS bulk 65-nm static random access memories (SRAMs) subjected to fusion neutrons during deuterium–deuterium (D-D) plasma operation at W–tungsten–Environment in Steady-state Tokamak (WEST). The test equipment, installed in the experimental hall at several locations of the tokamak, was irradiated during machine shots by a flux of particles dominated by primary 2.45-MeV neutrons. Real-time neutron metrology, neutron spectrometry, complementary characterization with monoenergetic neutrons, and Monte Carlo numerical simulations at both material and circuit levels have also been performed to analyze the experimental data. Our results suggest that higher energy neutrons, simultaneously produced by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, play a significant role in the radiation response of SRAMs for which multiple cell upsets are detected and cannot be attributed to D-D neutrons.

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

This article presents an analysis of the multiple events [and more specifically, multiple-cell upsets (MCUs)] that may occur at successive generations of bulk CMOS static random access memories (SRAMs) operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS)/International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90- and 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various commercial-off-the-shelf (COTS) SRAMs manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45 down to 14 nm).

Emulating Radiation-Induced Multicell Upset Patterns in SRAM FPGAs With Fault Injection

Radiation-induced multiple-cell upsets (MCUs) are events that account for more than 50% of failures on triple modular redundancy (TMR) designs in SRAM field programmable gate array (FPGA). It is important to understand these events and their impact on FPGA designs to develop improved fault mitigation techniques. This article describes an enhanced fault injection (FI) method for SRAM-based FPGAs that injects MCUs within the configuration memory of an FPGA based on MCU information extracted from previous radiation tests. The improved FI technique uncovers 3× more failures than is observable in conventional single-bit FI approaches. The results from several MCU FI experiments also show that injecting MCUs can replicate the failures observed in the radiation beam test and identify new failure mechanisms.

Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization With Neutrons and Alpha Particles

Negative and positive muon-induced single-event upsets (SEUs) are studied in 20-nm bulk planar SRAMs. Muon irradiation is performed using a mono-energetic source with varying the muon energy. The energy dependence of the cross sections (CSs) of SEUs and multiple-cell upsets (MCUs) shows the significant contribution of muon capture reactions for the negative muon, as reported in previous studies. Interestingly, MCU events are found for the positive muon, in contrast to the previous studies. The CSs for the negative and positive muons are compared with that for the other terrestrial radiations: high-energy neutrons, thermal neutrons, and alpha particles. The voltage dependence of the SEU CS, together with the empirical model for charge collection, demonstrates the difference in the contributing secondary ions among the negative muon, the high-energy neutron, and the thermal neutron. The MCU events are thoroughly analyzed in terms of their ratio to the total events and their fail bit patterns. The results reveal that the MCU characteristics for the negative muon are different from that for the other terrestrial radiations due to the muon capture reactions, where parasitic bipolar effects and the isotropic emission of secondary ions are important factors.

TIARA: Industrial Platform for Monte Carlo Single-Event Simulations in Planar Bulk, FD-SOI, and FinFET

In this article, we present Tool suIte for rAdiation Reliability Assessment (TIARA), an industrial version of a Monte Carlo single-event simulation platform, enabling fast and accurate soft error rate (SER) estimations. This tool is capable of simulating logic cells manufactured in several technologies such as fully depleted silicon on insulator (FD-SOI), FinFET, and planar bulk CMOS. Moreover, TIARA is able to handle many different types of radiations including by-products of neutron or proton spallation, heavy ions and alpha particles, representative of terrestrial and space environments. Three use cases are shown in this article to illustrate TIARA capabilities. The first one compares the error rate in Geostationary Earth Orbit (GEO) orbit of all flip-flop variants from a 28-nm FD-SOI library. Second one evaluates multiple-cell upsets as a function of simulated array size for static random access memory (SRAM) cells manufactured in a 40-nm bulk technology. The last one shows alpha and neutron SER results for SRAM designed in a bulk-FinFET technology.

Impact of TMR design layouts on single event tolerance in SRAM-based FPGAs

For highly reliable applications in mission critical systems, the Triple Modular Redundancy (TMR) technique is believed to be a common and effective approach to mitigate Single Event Upsets (SEUs) in Field Programmable Gate Arrays (FPGAs). In one of our neutron test campaigns, we observed an increase of 53.8% in single event tolerance of our optimized Fast Fourier Transform (FFT) design compared with the baseline (i.e., the traditional FFT design), while the increase of the TMR'd optimized FFT design is only 30.8% compared with the baseline. Although it is believed that Multiple-Cell Upsets (MCUs) poses a negative impact on the single event performance of TMR, the results of the TMR'd optimized FFT design are far from our expectations. A large number of preliminary simulations confirm that layout changes have a significant impact on the Multiple-Bit Upsets (MBUs) sensitivity of TMR'd design. This is because in the layout obtained through automatic placement and routing, these replicated modules of the TMR are interlaced with each other. Therefore, MBUs are more likely to induce domain-crossing events and affect two or more TMR modules. To further harden the TMR'd design, either putting three identical circuits of the TMR'd design into three independent blocks or using Dynamic Partial Reconfiguration (DPR) is demonstrated effective in mitigating MBUs in Static Random-Access Memory (SRAM)-based FPGAs.

The Influence of Ion Track Characteristics on Single-Event Upsets and Multiple-Cell Upsets in Nanometer SRAM

The influence of ion track characteristics on single-event upsets (SEU) and multiple-cell upsets (MCUs) is investigated in 65-nm static randon access memory (SRAM) above the heavy-ion linear energy transfer (LET) threshold. The experimental results show that for the incident heavy ions with the same or similar LET but different energies, SEU cross section of low-energy ions is higher than high-energy ions when the LET values are located below the knee point of low-energy SEU event cross section curves. With the LET values increasing above the knee point, SEU cross section of high-energy ions is higher than low-energy ions. When the effective LETs of different-energy ions within the sensitive region are the same, MCU mean, MCU ratio, and MCU event cross sections of high-energy ions are greater than those of low-energy ions due to larger track radius. During the test evaluation of heavy-ion single-event effect (SEE) in nanometer devices, it may be advisable that the SEU LET threshold be obtained with low-energy ions and the SEU saturation cross section be obtained with high-energy ions.

Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range* *Project supported by the Major Program of the National Natural Science Foundation of China (Grant Nos. 11690043 and 11690040).

The influences of reducing the supply voltage on single event upset (SEU) and multiple-cell upset (MCU) in two kinds of 65-nm static random access memories (SRAMs) are characterized across a wide linear energy transfer (LET) range. The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6T SRAM or radiation-hardened double dual interlocked cells (DICE) SRAM. When the LET value is lower than the LET threshold of MCU, the SEU only manifests single cell upset, the SEU cross section increases with the decrease of voltage. The lower the LET value, the higher the SEU sensitivity to the voltage variation is. Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU. Moreover, the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range. With further scaling the feature size of devices down, it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf (COTS) SRAM.

Evaluation of a COTS 65-nm SRAM Under 15 MeV Protons and 14 MeV Neutrons at Low VDD

This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on standby and while reading the memory. Results show obvious evidence indicating that decreasing the bias voltage below 1 V exponentially increases the number of observed errors. Single-bit upsets (SBUs) and multiple-cell upsets (MCUs) (mostly with vertical shapes according to the manufacturers’ layout) are reported and their behavior is analyzed in this article. Predictions on the single-event upset (SEU) sensitivity obtained with the multiscales single-event phenomena predictive platform (MUSCA-SEP3) modeling tool are also provided and compared with the experimental results. These are also compared with 14.2 MeV neutrons, showing a significant difference in the cross sections for both irradiation sources. Total ionizing dose (TID) tests and GEANT4 simulations were also run to check for the reason behind the difference in the cross section between these two particles.