New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application

Abstract

Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the reliability of static random access memories (SRAMs) in space application. Due to radiation, single cell or multiple cells of a memory are corrupted. The chances of errors in more than one memory cells are also increasing due to continuous down scaling of technology. Single error, double or triple adjacent errors are most common in this case. Several error correction codes are already introduced for protecting the memories. But many existing error correcting codes have either higher delay and/or power consumption and/or decoder error rate. In this paper, we have introduced 16-bit, 32-bit and 64-bit information length, uniquely decodable single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes with lower power consumption and delay. In our design, same H-matrix is used for implementing both SEC-DAEC and SEC-DAEC-TAEC codes. Both FPGA and ASIC based synthesis results show that proposed SEC-DAEC and SEC-DAEC-TAEC codes with dimensions (24, 16), (41, 32) and (75, 64) are better compared to existing same dimension codes with respect to area, power and delay. Since, the proposed SEC-DAEC and SEC-DAEC-TAEC codes have low encoder and decoder delay which corresponds to low writing and reading time, consume significantly low power and have zero decoder error rate, so proposed codec can be used for memories in space application.