Multilevel Nonvolatile Memory Research Articles

An Ultrafast Multibit Memory Based on the ReS2/h-BN/Graphene Heterostructure.

The exponential growth of data in the big data era has made it imperative to improve the data storage density and calculation speed. Therefore, the development of a multibit memory with an ultrafast operational speed is of great significance. In this work, a floating-gate (FG) memory based on the ReS2/h-BN/graphene van der Waals heterostructure is reported. The device exhibits ultrafast and multilevel nonvolatile memory characteristics, notably featuring an exceptionally large memory window of 113.36 V, a substantial erasing/programming current ratio of 107, an ultrafast operational speed of 30 ns, outstanding endurance exceeding 1000 cycles, and retention performance exceeding 1100 s. Furthermore, the device exhibits both electrically and optically tunable multilevel nonvolatile memory behavior. By controlling the voltage and light pulse parameters, the device achieves an electrical memory state of 130 levels (>7 bits) and an optical memory state of 45 levels (>5 bits).

Programmable Optoelectronic Synaptic Transistors Based on MoS2/Ta2NiS5 Heterojunction for Energy-Efficient Neuromorphic Optical Operation.

The optoelectronic synaptic transistors with various functions, broad spectral perception, and low power consumption are an urgent need for the development of advanced optical neural network systems. However, it remains a great challenge to realize the functional diversification of the systems on a single device. 2D van der Waals (vdW) materials can combine unique properties by stacking with each other to form heterojunctions, which may provide a strategy for solving this problem. Herein, an all-2D vdW heterojunction-based programmable optoelectronic synaptic transistor based on MoS2/Ta2NiS5 heterojunctions is demonstrated. The device implements reconfigurable, multilevel non-volatile memory (NVM) states through sequential modulation of multiple optical and electrical stimuli to achieve broadband (532-808nm), energy-efficient (17.2 fJ), hetero-synaptic functionality in a bionic manner. The intrinsic working mechanisms of the photogating effect caused by band alignment and the interfacial trapping defect modulation induced by gate voltage are revealed by Kelvin-probe force microscopy (KPFM) measurements and carrier transport analysis. Overall, the (opto)electronic synaptic weight controllability for combined in-sensor and in-memory logic processors is realized by the heterojunction properties. The proposed findings facilitate the technical realization of generic all 2D hetero-synapses for future artificial vision systems, opto-logical systems, and Internet of Things (IoT) entities.

Applying the Wake-Up-like Effect to Enhance the Capabilities of Two-Dimensional Ferroelectric Field-Effect Transistors.

For traditional ferroelectric field-effect transistors (FeFETs), enhancing the polarization domain of bulk ferroelectric materials is essential to improve device performance. However, there has been limited investigation into the enhancement of polarization field in two-dimensional (2D) ferroelectric material such as CuInP2S6 (CIPS). In this study, similar to bulk ferroelectric materials, CIPS exhibited enhanced polarization field upon application of external cyclic voltage. Moreover, unlike traditional ferroelectric materials, the polarization enhancement of CIPS is not due to redistribution of the defect but rather originates from a mechanism: the long-distance migration of Cu ions. We termed this mechanism the "wake-up-like effect". After incorporating the wake-up-like effect into the graphene/CIPS/WSe2 FeFET device, we successfully increased the hysteresis window and enhanced the current on/off ratio by 4 orders of magnitude. Moreover, the FeFET yielded remarkable achievements, such as multilevel nonvolatile memory with 21 distinct conductance levels, a high on/off ratio exceeding 106, a long retention time exceeding 103 s, and neuromorphic computing with 93% accuracy at recognizing handwritten digits. Introducing the wake-up-like effect to 2D CIPS may pave the way for innovative approaches to achieve advanced multilevel nonvolatile memory and neuromorphic computing capabilities for next-generation micro-nanoelectronic devices.

Emergence of Ferroelectricity in p‐Type 2D In1.75Sb0.25Se3

p‐type 2D ferroelectric semiconductors (2D FeSs) play an increasingly essential role in the advanced nonvolatile and morphotropic beyond‐Moore electronic devices with high performance and low power consumption. But reliable p‐type 2D FeS with holes as majority carriers are still scarce. Herein, the first experimental realization of room‐temperature ferroelectricity in van der Waals layered β‐In1.75Sb0.25Se3 down to few layer is reported. The origin of ferroelectricity in β‐In1.75Sb0.25Se3 comes from aliovalent elemental substitution, antimony substituting to the indium sites (SbIn), changing the local environment of the central‐layer Se atoms. Thanks to the intrinsic ferroelectric and semiconducting natures, FeS field‐effect transistor (FeSFET) devices based on β‐In1.75Sb0.25Se3 exhibit reconfigurable, multilevel nonvolatile memory (NVM) states, which can be successively modulated by gate voltage stimuli. Furthermore, the inherent operation mechanism, due to the switchable polarization, indicates that a neuromorphic memory is also possible with 2D FeSFETs. These presented results facilitate the technological implementation of versatile 2D FeS devices for next‐generation logic‐in‐memory approach for Internet‐of‐Things entities.

Dynamics of Analog Switching Behavior in Thin Polycrystalline Barium Titanate

AbstractEngineering of interfaces and point defects in ferroelectric memristors is an efficient way for manipulating the resistive switching effects of mixed ionic‐electronic nature. However, an interplay between the defects, interfacial properties, and ferroelectric polarization as well as their influence on the resistance state tuning are yet to be revealed. By considering the memristive device built on a thin polycrystalline BaTiO3 film, a drift‐diffusion model of non‐stationary processes is developed. The model is based on Poisson and continuity equations solved numerically and accounts for various transport mechanisms for electrons, holes, and oxygen vacancies. Comparing simulated resistive effects with experimental data taken in a wide temperature range, it is shown that an appearance of the analog resistive switching cannot be explained solely by oxygen‐ionic transport. Investigated switching dynamics claims the oxygen vacancies redistribution to be responsible for the analog character of the switching at the prevalence of the electron hopping transport. Crucially, the required dynamics of the vacancies redistribution is achieved only in a narrow range of their mobility. These results can be used in designing the ferroelectric memristors for nonvolatile multilevel memory devices satisfying the requirements that arise at the stages of their integration into neuromorphic architectures.

Giant tunnelling electroresistance in atomic-scale ferroelectric tunnel junctions

Ferroelectric tunnel junctions are promising towards high-reliability and low-power non-volatile memories and computing devices. Yet it is challenging to maintain a high tunnelling electroresistance when the ferroelectric layer is thinned down towards atomic scale because of the ferroelectric structural instability and large depolarization field. Here we report ferroelectric tunnel junctions based on samarium-substituted layered bismuth oxide, which can maintain tunnelling electroresistance of 7 × 105 with the samarium-substituted bismuth oxide film down to one nanometer, three orders of magnitude higher than previous reports with such thickness, owing to efficient barrier modulation by the large ferroelectric polarization. These ferroelectric tunnel junctions demonstrate up to 32 resistance states without any write-verify technique, high endurance (over 5 × 109), high linearity of conductance modulation, and long retention time (10 years). Furthermore, tunnelling electroresistance over 109 is achieved in ferroelectric tunnel junctions with 4.6-nanometer samarium-substituted bismuth oxide layer, which is higher than commercial flash memories. The results show high potential towards multi-level and reliable non-volatile memories.

High-performance multilevel nonvolatile organic field-effect transistor memory based on multilayer organic semiconductor heterostructures

A multilevel organic field-effect transistor memory based on organic heterostructures is demonstrated. Benefiting from the charge trapping of the quantum well-like heterostructures, the memory exhibited multilevel nonvolatile memory properties.

Multilevel resistance states in van der Waals multiferroic tunnel junctions above room temperature

Multiferroic tunnel junctions (MFTJs) comprised of magnetic electrodes and a ferroelectric tunnel barrier have been emerging as promising candidates for nonvolatile memory applications. The recently discovered above room-temperature van der Waals (vdW) ferromagnet Fe3GaTe2 and ferroelectric α-In2Se3 provides possibilities for constructing room-temperature vdW MFTJs. In this work, by using first-principles calculations, we investigate the spin-dependent transport in vdW MFTJs with structure of Fe3GaTe2/bilayer α-In2Se3/Fe3GaTe2. We predict a giant tunneling magnetoresistance (TMR) high up to 10 000% by switching the magnetic alignments of Fe3GaTe2 and tunneling electroresistance (TER) exceeding 300% by controlling the ferroelectric configurations of bilayer α-In2Se3 in the proposed MFTJs. Furthermore, by introducing interface asymmetry and inserting monolayer of h-BN on one interface, the TMR and TER ratios of the MFTJs can be substantially enhanced. In consequence, the multi-level resistance states can be achieved by applying magnetic and electric field in asymmetric MFTJs. Our results highlight full vdW MFTJs for their potential applications in spintronic devices, particularly in the field of multilevel nonvolatile memories.

Thermally Driven Multilevel Non-Volatile Memory with Monolayer MoS2 for Brain-Inspired Artificial Learning.

The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities toward developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS2 memtransistors, which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multilevel memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS2/dielectric interface. We have proposed a non-volatile memory application using a single Field Effect Transistor (FET) device where thermal energy can be ventured to aid the memory functions with multilevel (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way toward reliable data processing and storage using 2D semiconductors with high-packing density arrays for brain-inspired artificial learning.

3D trigonal FAPbI3‐based multilevel resistive switching nonvolatile memory for artificial neural synapse

AbstractHybrid perovskites have attracted enormous attention in the next generation resistive switching (RS) memristor for the artificial synapses, owing to their ambipolar charge transport, long diffusion length, and tunable visible bandgap. However, the variable switch, limited reproducibility, and poor endurance are the obstacles to the practical application of the perovskite memristors. Herein, we reported a multilevel RS nonvolatile memory based on a 3D trigonal HC(NH2)2PbI3 (α‐FAPbI3) perovskite layer modified by 1‐cyanobutyl‐3‐methylimidazolium chloride ([CNBmim]Cl) and sandwiched between ITO and Au electrodes (Au/[CNBmim]Cl/α‐FAPbI3/SnO2/ITO). In contrast to the bare memristor with failure switching from low resistance state (LRS) to high resistance state (HRS), the memristor device based on the α‐FAPbI3 modified with [CNBmim]Cl (Target device) shows the retention time over 104 s with On/Off ratio (>102) and endurance up to 550 cycles. The stable RS cycle benefits from the accelerated electrons de‐trapping from the reduced defects and fast charge separation in the interface of α‐FAPbI3/electrode, leading to the rupture of conductive filaments and transition of LRS to HRS. As a two‐terminal analog synaptic device, the target device can realize random handwritten digit recognition with an impressive accuracy of 89.3% on the condition of low learning phases (500 training cycles).

High-Performance C60 Coupled Ferroelectric Enhanced MoS2 Nonvolatile Memory.

Nonvolatile memory (NVM) devices based on two-dimensional (2D) materials have recently attracted widespread attention due to their high-density integration potential and the ability to be applied in computing-in-memory systems in the post-Moore era. Considering the high current on/off ratio, programmable threshold voltage, nonvolatile multilevel memory state, and extended logic functions, plenty of breakthroughs related to ferroelectric field-effect transistors (FeFETs), one of the most important NVM devices, have been made in the past decade. Among them, FETs coupled with organic ferroelectric films such as P(VDF-TrFE) displayed properties of remarkable robustness, easy preparation, and low cost. However, the dipoles of the P(VDF-TrFE) film cannot be flipped smoothly at low voltage, impeding the further application of organic FeFET. In this paper, we proposed a high-performance FeFET based on monolayer MoS2 coupled with C60 doped ferroelectric copolymer P(VDF-TrFE). The inserted C60 molecules enhanced the alignment of the dipoles effectively at low voltage, allowing the modified device to demonstrate a large memory window (∼16 V), high current on/off ratio (>106), long retention time (>10 000 s), and remarkable endurance under the reduced operating voltage. In addition, the in situ logic application can be realized by constructing facile device interconnection without building complex complementary semiconductor circuits. Our results are expected to pave the way for future low-consumption computing-in-memory applications based on high-quality 2D FeFETs.

Tri-level resistive switching characteristics and conductive mechanism of HfO<sub>2</sub>/NiO<sub><i>x</i></sub>/HfO<sub>2</sub> stacks

<sec>With the extensive integration of portable computers and smartphones with “Internet of Things” technology, further miniaturization, high reading/writing speed and big storage capacity are required for the new-generation non-volatile memory devices. Compared with traditional charge memory and magnetoresistive memory, resistive random access memory (RRAM) based on transition metal oxides is one of the promising candidates due to its low power consumption, small footprint, high stack ability, fast switching speed and multi-level storage capacity.</sec><sec>Inspired by the excellent resistive switching characteristics of NiO and HfO<sub>2</sub>, NiO<sub><i>x</i></sub> films are deposited by magnetron sputtering on the Pt<inline-formula><tex-math id="Z-20230629144836">\begin{document}$\langle111\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144836.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144836.png"/></alternatives></inline-formula> layer and the polycrystalline HfO<sub>2</sub> film, respectively. Their microstructures, resistive switching characteristics and conductive mechanisms are studied. X-ray diffractometer data show the <inline-formula><tex-math id="Z-20230629144852">\begin{document}$\langle111\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144852.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144852.png"/></alternatives></inline-formula> preferred orientation for the NiO<sub><i>x</i></sub> film deposited on the Pt<inline-formula><tex-math id="Z-20230629144904">\begin{document}$\langle111\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144904.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144904.png"/></alternatives></inline-formula> layer but the <inline-formula><tex-math id="Z-20230629144913">\begin{document}$\langle100\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144913.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230629144913.png"/></alternatives></inline-formula> preferred one for the film deposited on the polycrystalline HfO<sub>2</sub> layer. X-ray photoelectron depth profile of Ni 2p core level reveals that the NiO<sub><i>x</i></sub> film is the mixture of oxygen-deficient NiO and Ni<sub>2</sub>O<sub>3</sub>. NiO<sub><i>x</i></sub>(111) films show bipolar resistive switching (RS) characteristics with a clockwise current-voltage (<i>I-V</i>) loop, but its ratio of the high resistance to the low resistance (<i>R</i><sub>H</sub>/<i>R</i><sub>L</sub>) is only ~10, and its endurance is also poor. The NiO<sub><i>x</i></sub>(200)/HfO<sub>2</sub> stack exhibits bipolar RS characteristics with a counterclockwise <i>I-V</i> loop. The <i>R</i><sub>H</sub>/<i>R</i><sub>L</sub> is greater than 10<sup>4</sup>, the endurance is about 10<sup>4</sup> cycles, and the retention time exceeds 10<sup>4</sup> s. In the initial stage, the HfO<sub>2</sub>/NiO<sub><i>x</i></sub>(200)/HfO<sub>2</sub> stack shows similar bi-level RS characteristics to the NiO<sub><i>x</i></sub>(200)/HfO<sub>2</sub> stack. However, in the middle and the last stages, its <i>I-V</i> curves gradually evolve into tri-level RS characteristics with a “two-step Setting process” in the positive voltage region, showing potential applications in multilevel nonvolatile memory devices and brain-like neural synapses. Its <i>I-V</i> curves in the high and the low resistance state follow the relationship of ohmic conduction (<inline-formula><tex-math id="Z-20230714031758-1">\begin{document}$ I \propto V $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230714031758-1.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230714031758-1.png"/></alternatives></inline-formula>), while the <i>I-V</i> curves in the intermediate resistance state are dominated by the space-charge-limited-current mechanism (<inline-formula><tex-math id="Z-20230714031758-2">\begin{document}$ I \propto V^2 $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230714031758-2.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="14-20230331_Z-20230714031758-2.png"/></alternatives></inline-formula>). The tri-level RS phenomena are attributed to the coexistence of the oxygen-vacancy conductive filaments in the NiO<sub><i>x</i></sub>(200) film and the space charge limited current in the upper HfO<sub>2</sub> film.</sec>

Ferroelectric FDSOI FET modeling for memory and logic applications

In this paper, we present a Verilog-A based compact model for simulating Ferroelectric Fully Depleted Silicon-on-Insulator (Fe-FDSOI) FET. The model can capture the rich physics of ferroelectric (FE) materials and reproduce the important electrical characteristics, such as history effect, the impact of threshold voltage on pulse width and amplitude as well as potentiation–depression characteristics. The FE switching is modeled using Preisach model to capture the Polarization (P)–Voltage (V) characteristics. In addition, we capture the history-dependent minor loop characteristics to obtain multiple states of polarization. This allows the modeling of multiple conductance states, which forms the fundamental prerequisite for neuromorphic applications as well as multi-level non-volatile memories. The underlying baseline FDSOI FET is modeled using the industry-standard BSIM-IMG compact model. The model is then augmented with the physics-based model of FE capacitor to realize Fe-FDSOI FET. Our model is computationally efficient and carefully calibrated to reproduce experimental measurement data.

A novel ferroelectric nanopillar multi-level cell memory

In this work, we present a novel multi-level non-volatile memory (NVM) device where ferroelectric (FE) nanopillars are embedded in a dielectric (DE) medium. Using our in-house 3D phase field simulator developed to treat the FE–DE composite system stably, we demonstrate that n FE nanopillars can generate more than 2n states, enabling high storage capacity. The multistates of the pillar array device are attributed to the depolarization field modulation with the pillar height and the multi-domain topological states of nanoscale FE structures.

La-doped BiFeO3 junction based random access multilevel nonvolatile memory

Resistive switching devices are promising candidates for the next generation nonvolatile memories due to their outstanding performance, simplicity, and scalability. Among them, developing multilevel resistive switching has attracted great attention for its potential in significantly improving information storage density but without extra energy consumption. Although continuous multilevel resistive switching (CMRS) has been observed in many metal oxides and organic materials, achieving random access multilevel nonvolatile memories (RAMNM) with high speed and reliability is still pressingly needed for practical applications. Here, we have successfully fabricated a RAMNM based on high–performance pulse-width modulated memristive ferroelectric tunnel junctions (FTJs) of Pt/La0.1Bi0.9FeO3/Nb:SrTiO3 with giant switching ratios above 4 × 105 at room temperature.

Graphene oxide enhanced phase change tolerance of Ge2Sb2Se4Te1 for all-optical multilevel non-volatile photonics memory

The low optical loss of G e 2 S b 2 S e 4 T e 1 (GSST) makes it a potential functional material for all-optical multilevel photonics memory devices that can operate in the optical telecommunication wavelength band. However, the same characteristic also restricted the tolerance of GSST phase change conditions using 1550 nm as an excitation light source. This work reports on the enhancement of GSST phase change condition tolerance using a graphene oxide (GO) intermediate layer on a polymer waveguide platform. The hybrid waveguide exhibits an insertion loss of around 1 dB and a maximum readout contrast of 25% between amorphous and crystalline states, with a step increase in readout contrast of around 5% per step. This work serves as a proof of concept for the implementation of a GSST–GO hybrid structure as an optical functional material in all-optical photonics memory applications.

Optically Encodable and Erasable Multilevel Nonvolatile Flexible Memory Device Based on Metal-Organic Frameworks.

Multilevel and flexible nonvolatile memory (NVM) is a promising candidate for data storage in next-generation devices but its high bias and low mobility of conducting channels are often its drawbacks. In this study, we demonstrate a low bias of smaller than 0.1 V and a high-mobility graphene layer as a conducting channel for flexible optoelectronic NVM based on a composite thin film of indium-based MOF-derived InCl3 and 4,4-oxydiphthalic anhydride (odpta), Na[In3(odpt)2(OH)2(H2O)2](H2O)4, and reduced graphene oxide (rGO). The optoelectronic NVM device can be encoded and erased optically by ultraviolet (UV) light and visible light, respectively. Our device also achieves memory states over 192 (6-bit storage) distinct levels, which can emerge as mass data storage. It also shows an excellent endurance of write-erase cycles under irradiation with a laser of varying wavelengths, the mechanical stability of more than 1000 bending cycles, and stable retention for longer than 10 000 s. These results open an alternative route for developing low bias and innovative optoelectronic technologies.

Defect generation in a data-storage layer by strong ion bombardment for multilevel non-volatile memory applications

Neuromorphic devices and systems have been widely studied for future computing platforms. For an accurate neural network, each memory cell in the system requires multilevel data to support sufficient weight levels. However, conventional memory devices have limitations in increasing the data levels while maintaining low power consumption. In this study, we demonstrate that a strong ion bombardment process can be a viable solution for multilevel memory. During sputter deposition of a data-storage layer in charge trap flash, a substrate bias increases the total trap density by 64%, which significantly enhances the memory window and data levels. From secondary ion mass spectrometry and X-ray photoelectron spectroscopy, we reveal that the origin of the increase in trap states is the ejection of O atoms by the bombardment process. The present work provides a novel strategy to increase the data levels of a memory device, and thus, paves the way for reliable neuromorphic hardware system.

Multilevel memory and artificial synaptic plasticity in P(VDF-TrFE)-based ferroelectric field effect transistors

Multilevel data memory and artificial synaptic plasticity in poly(vinylidene fluoride-co-trifluoroethylene) [P(VDF-TrFE)] ferroelectric field effect transistors were demonstrated. The dynamics of ferroelectric polarization transformation modulate potential of transistor channel, and adjust the electric field of the P(VDF-TrFE) ferroelectric film by potential along channel direction, thus realizing the multilevel nonvolatile memory state. The artificial synaptic plasticity of transistor is simulated, and the long-term plasticity of excited/inhibited postsynaptic current, paired impulse facilitation/inhibition, and spike-rate-dependent plasticity is realized. In long-term potentiation/depression simulation of devices, the conductivity symmetry and linearity are improved by setting the amplitude of the pulse increments. In addition, the vector-matrix multiplication operation was performed in a crossbar array. This work demonstrates the scheme to develop the P(VDF-TrFE) transistors-based multilevel memory and neural morphological computing.

Energy-efficient non-volatile ferroelectric based electrostatic doping multilevel optical readout memory.

Non-volatile multilevel optical memory is an urgent needed artificial component in neuromorphic computing. In this paper, based on ferroelectric based electrostatic doping (Fe-ED) and optical readout due to plasma dispersion effect, we propose an electrically programmable, multi-level non-volatile photonics memory cell, which can be fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. Hf0.5Zr0.5O2 (HZO) film is chosen as the ferroelectric ED layer and combines with polysilicon layers for an enhanced amplitude modulation between the carrier accumulation and the confined optical field. Insertion loss below 0.4 dB in erasing state and the maximum recording depth of 9.8 dB are obtained, meanwhile maintaining an extremely low dynamic energy consumption as 1.0-8.4 pJ/level. Those features make this memory a promising candidate for artificial optical synapse in neuromorphic photonics and parallel computing.