Multilevel Nonvolatile Memory Research Articles

Insights into Multilevel Resistive Switching in Monolayer MoS2.

The advent of two-dimensional materials has opened a plethora of opportunities in accessing ultrascaled device dimensions for future logic and memory applications. In this work, we demonstrate that a single layer of large-area chemical vapor deposition-grown molybdenum disulfide (MoS2) sandwiched between two metal electrodes can be tuned to show multilevel nonvolatile resistive memory states with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven requiring significant Joule heating in the reset process. Temperature-dependent electrical measurements coupled with semiclassical charge transport models suggest that the transport in these devices varies significantly in the initial (pristine) state, high resistance state, and low resistance state. In the initial state, the transport is a one-step direct tunneling (at low voltage biases) and Fowler Nordeim tunneling (at higher bias) with an effective barrier height of 0.33 eV, which closely matches the Schottky barrier at the MoS2/Au interface. In the high resistive state, trap-assisted tunneling provides a reasonable fit to experimental data for a trap height of 0.82 eV. Density functional theory calculations suggest the possibility of single- and double-sulfur vacancies as the microscopic origins of these trap sites. The temperature-dependent behavior of the set and reset process are explained by invoking the probability of defect (sulfur vacancy) creation and mobility of sulfur ions. Finally, conductive atomic force microscopy measurements confirm that the multifilamentary resistive memory effects are inherent to a single-crystalline MoS2 triangle and not necessarily dependent on grain boundaries. The insights suggested in this work are envisioned to open up possibilities for ultrascaled, multistate, resistive memories for next-generation digital memory and neuromorphic applications.

Nonvolatile Memory and Artificial Synapse Based on the Cu/P(VDF-TrFE)/Ni Organic Memtranstor.

We demonstrate a flexible nonvolatile multilevel memory and artificial synaptic devices based on the Cu/P(VDF-TrFE)/Ni memtranstor which exhibits pronounced nonlinear magnetoelectric effects at room temperature. The states of the magnetoelectric voltage coefficient αE of the memtranstor are used to encode binary information. By applying selective electric-field pulses, the states of αE can be switched repeatedly among 2n states (n = 1, 2, 3) in a zero dc bias magnetic field. In addition, the magnetoelectric coefficient is used to act as synaptic weight, and the induced magnetoelectric voltage VME is regarded as postsynaptic potentials (excitatory or inhibitory). The artificial synaptic devices based on the Cu/P(VDF-TrFE)/Ni memtranstor display the long-term potentiation (depression) and spiking-time-dependent plasticity behaviors. The advantages of a simple structure, flexibility, multilevel, and self-biasing make the Cu/P(VDF-TrFE)/Ni organic memtranstor a promising candidate for applications in nonvolatile memory as well as artificial synaptic devices with low energy consumption.

Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new multi time programmable (MTP) cells exhibit tight threshold voltage distributions for multi-level cells (MLC) operations. Improved cycling reliability and one-shot multi-level programming has been fully demonstrated in this work.

Multilevel memory and synaptic characteristics of a-IGZO thin-film transistor with atomic layer–deposited Al2O3/ZnO/Al2O3 stack layers

Abstract

Multilevel nonvolatile memory based on the hysteretic giant magnetoimpedance effect of heterogeneous magnetic laminate

This work investigates the asymmetric and hysteretic GMI effect of two-phase heterogeneous magnetic laminate consisting of Ni/Fe30Ni45Co18Si2B5/micro-planar coil/Fe30Ni45Co18Si2B5/Ni for nonvolatile memory application. Since the magnetostrictive Ni ribbon produces the remanent magnetoelastic and magnetostatic fields to the neighboring soft amorphous magnetic alloy (Fe30Ni45Co18Si2B5) when the external dc magnetic field is removed, the proposed laminate manifests multi-level remanent impedances depending on the previously applied magnetic field. And the maximum nonvolatile GMI ratio of 130% is obtained at 400 kHz frequency. Furthermore the laminate can function as multilevel nonvolatile memory, which consumes zero standby power without losing data.

Ferroelectric materials for neuromorphic computing

Ferroelectric materials are promising candidates for synaptic weight elements in neural network hardware because of their nonvolatile multilevel memory effect. This feature is crucial for their use in mobile applications such as inference when vector matrix multiplication is performed during portable artificial intelligence service. In addition, the adaptive learning effect in ferroelectric polarization has gained considerable research attention for reducing the CMOS circuit overhead of an integrator and amplifier with an activation function. In spite of their potential for a weight and a neuron, material issues have been pointed out for commercialization in conjunction with CMOS processing and device structures. Herein, we review ferroelectric synaptic weights and neurons from the viewpoint of materials in relation to device operation, along with discussions and suggestions for improvement. Moreover, we discuss the reliability of HfO2 as an emerging material and suggest methods to overcome the scaling issue of ferroelectrics.

Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights

We present a fully CMOS-compatible multi-level non-volatile memory technology, without any special process cost. It is especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency. We use hot carrier injection to program the single-transistor cells, and we conduct charge pumping experiments which identify interfacial traps, rather than bulk oxide traps, as the dominant factor in producing stable $I-V$ shifts. We also derive a new physics-based experimentally verified logarithmic model to explain the rate of interfacial trap generation in large $I-V$ shift regimes where the conventional power-law no longer applies. We fabricate two chips, one using TSMC’s 16 nm FinFET and the other in 28 nm planar, and show the FinFET cells are more favorable for non-volatile memory due to their better channel control. We store multiple levels in each FinFET cell using a “program and check” strategy which sets memory cells’ currents with standard deviations less than $2~{\mu }A$ across a shifting range of over $100~{\mu }A$ . We demonstrate 8 level FinFET cells with extrapolated 10-year charge loss within 10% at 125 °C.

Crossover of polar and toroidal orders in ferroelectric nanodots with a morphotropic phase boundary and nonvolatile polar-vortex transformations

Ferroelectric vortices are promising candidates for developing high-capacity memory devices and discovery of intriguing electromechanical properties. It is well known that the ferroelectric vortex state tends to stabilize at poor screening conditions and a relatively good screening condition would give rise to a polar state. However, what happens at the intermediate screening condition remains unclear. In this work, by including a Bardeen screening model into phase-field simulations, we explore the screening-mediated state stabilization in ferroelectric nanodots. A state coexistence regime where the polar and toroidal orders can both stabilize in a ferroelectric nanodot is found at certain range of screening (that is, screening length from 0.011 to 0.022 nm at room temperature). The mechanism of state coexistence is analyzed by construction of the input-dependent free-energy profile according to the energy minimum principle. The coexistence regime is further revealed to be tunable by geometrical parameters. Importantly, the polar and vortex states can be readily switched between each other via electrical and mechanical loads, paving the way towards a type of nonvolatile multilevel memory. Moreover, a screening-mediated morphotropic phase boundary (MPB) with strong dielectric and piezoelectric responses is demonstrated. Our study thus discovers a stability crossover of polar and toroidal orders in ferroelectric nanodots at intermediate screening condition accompanied with superior electromechanical properties and the feasibility in multilevel memory application.

Machine Learning Applied to a Variable Charge Atomistic Model for Cu/Hf Binary Alloy Oxide Heterostructures

Alloy oxide heterostructures are essential for a wide variety of energy applications, including anticorrosion coatings, bifunctional catalysis, energy storage, as well as emerging platforms for multilevel nonvolatile memory and neuromorphic devices. The key role played by oxide composition, density, and stoichiometry in governing electrochemical reactions, interface structure, and ionic transport in alloy oxides remains largely unknown. This is primarily due to the lack of variable charge interatomic potential models that can adequately describe the various atomic/ionic interactions in alloy oxides within a unified framework. Here, we introduce a charge transfer ionic potential (CTIP) model for Cu/Hf/O alloy system and demonstrate its ability to accurately capture the complex potential energy surface owing to dynamically varying interactions, including metallic (Cu/Hf), ionic (Cu/Hf/Ox), mixed environment (interfaces). We leverage supervised machine learning methods powered by genetic algorithms coupled with local simplex optimization to efficiently navigate through a high-dimensional parameter space and identify an optimum set of an independent set of CTIP parameters. We train our model against an extensive first-principles based data set that includes lattice constants, cohesive energies, equations of state, and elastic constants of various experimentally observed polymorphs of hafnia, copper oxide, hafnium, as well as copper. Our machine-learned CTIP model captures the structure, elastic properties, thermodynamics, and energetic ordering of various polymorphs. It also accurately predicts the surface properties of both oxides and their metals. To demonstrate the suitability of our CTIP model for investigating dynamic processes, we employed it to identify the atomistic scale mechanisms associated with the initial nanoscale oxidation and surface oxide growth on Cu-doped hafnia surfaces. Our machine-learned CTIP model can be used to probe the dynamic response of Cu/Hf/O alloy interfaces subjected to external stimuli (e.g., electric field, pressure, temperature, strain, etc.) and a variety of atomistic phenomena including the dynamics of switching in emerging neuromorphic platforms.

Two-Terminal Multibit Optical Memory via van der Waals Heterostructure.

2D van der Waals (vdWs) heterostructures exhibit intriguing optoelectronic properties in photodetectors, solar cells, and light-emitting diodes. In addition, these materials have the potential to be further extended to optical memories with promising broadband applications for image sensing, logic gates, and synaptic devices for neuromorphic computing. In particular, high programming voltage, high off-power consumption, and circuital complexity in integration are primary concerns in the development of three-terminal optical memory devices. This study describes a multilevel nonvolatile optical memory device with a two-terminal floating-gate field-effect transistor with a MoS2 /hexagonal boron nitride/graphene heterostructure. The device exhibits an extremely low off-current of ≈10-14 A and high optical switching on/off current ratio of over ≈106 , allowing 18 distinct current levels corresponding to more than four-bit information storage. Furthermore, it demonstrates an extended endurance of over ≈104 program-erase cycles and a long retention time exceeding 3.6 × 104 s with a low programming voltage of -10 V. This device paves the way for miniaturization and high-density integration of future optical memories with vdWs heterostructures.

Ten States of Nonvolatile Memory through Engineering Ferromagnetic Remanent Magnetization

AbstractEmerging nonvolatile multilevel memory devices have been regarded as a promising solution to meet the increasing demand of high‐density memory with low‐power consumption. In particular, decimal system of the new computers instead of binary system could be developed if ten nonvolatile states are realized. Here, a general remanent magnetism engineering method is proposed for realizing multiple reliable magnetic and resistance states, not depending on a specific material or device structure. Especially, as a proof‐of‐concept demonstration, ten states of nonvolatile memory based on the manipulation of ferromagnetic remanent magnetization have been revealed in both Co/Pt magnetic multilayers with strong perpendicular magnetic anisotropy and MgO‐based magnetic tunneling junctions at room temperature. Considering ferromagnets have been one of the key factors that enabled the information revolution from its inception, this state‐of‐the‐art remanent magnetism engineering approach has a very broad application prospect in the field of spintronics.

Bipolar resistive switching effects with self-compliance and multilevel storage characteristics in Ag/MgZnO/Si structures

In this work, we have fabricated the MgZnO thin films directly on low resistive silicon substrates by using a chemical solution deposition route. Besides the investigation of the structures, morphologies, chemical states, and photoluminescence properties of MgZnO thin films, the bipolar resistive switching behaviours have been evaluated in the simple Ag/MgZnO/Si structures. The self-compliance resistive switching characteristics simplify the device configuration and circuit design for practical applications. In addition, the multilevel storage capabilities have also been investigated by regulating different operation voltages or compliance currents, respectively. The four level storage capabilities show long retention time and good cycling performance. The resistive switching mechanism has been explicated by the formation and rupture of Ag filament based on the electrochemical metallization model. This work suggests that the Ag/MgZnO/Si structures have potential non-volatile multilevel memory applications.

Large-area plastic nanogap electronics enabled by adhesion lithography

Large-area manufacturing of flexible nanoscale electronics has long been sought by the printed electronics industry. However, the lack of a robust, reliable, high throughput and low-cost technique that is capable of delivering high-performance functional devices has hitherto hindered commercial exploitation. Herein we report on the extensive range of capabilities presented by adhesion lithography (a-Lith), an innovative patterning technique for the fabrication of coplanar nanogap electrodes with arbitrarily large aspect ratio. We use this technique to fabricate a plethora of nanoscale electronic devices based on symmetric and asymmetric coplanar electrodes separated by a nanogap < 15 nm. We show that functional devices including self-aligned-gate transistors, radio frequency diodes and rectifying circuits, multi-colour organic light-emitting nanodiodes and multilevel non-volatile memory devices, can be fabricated in a facile manner with minimum process complexity on a range of substrates. The compatibility of the formed nanogap electrodes with a wide range of solution processable semiconductors and substrate materials renders a-Lith highly attractive for the manufacturing of large-area nanoscale opto/electronics on arbitrary size and shape substrates.

A Constrained Coding Scheme for Correcting Asymmetric Magnitude-1 Errors in $q$ -Ary Channels

We present a constraint-coding scheme to correct asymmetric magnitude-1 errors in multi-level non-volatile memories. For large numbers of such errors, the scheme is shown to deliver better correction capability compared with known alternatives, while admitting low-complexity of decoding. Our results include an algebraic formulation of the constraint, necessary and sufficient conditions for correctability, a maximum-likelihood decoder running in complexity linear in the alphabet size, and upper bounds on the probability of failing to correct $t$ errors. Besides the superior rate-correction tradeoff, another advantage of this scheme over standard error-correcting codes is the flexibility to vary the code parameters without significant modifications.

Energy optimization for multi-level cell non-volatile memory using state remapping

Non-volatile Memory (NVM) is emerging as a promising technology to build future main memory or cache. Multi-level cell (MLC) NVM that stores multiple bits in a single cell has been developed in recent years. Different NVM technology has its own writing schemes to store multiple bits, and the amount of write energy varies across different states. For MLC Phase-Change Memory (PCM), the energy consumption of writing intermediate states, ‘01’ and ‘10’, is bigger than that of writing states ‘00’ and ‘11’. For MLC Spin-Transfer Torque Magnetic RAM (STT-MRAM), the energy consumption of flipping the left bit of a 2-bit cell is greater than that of flipping the right bit. To reduce the MLC NVM write energy consumption, we propose an encoding scheme to reduce the amount of intermediate states’ write for MLC PCM and another encoding scheme to decrease the number of the left bit flips for MLC STT-MRAM. The main idea of both schemes is state remapping. We find two minimum write frequency states and remap them to state ‘01’ and ‘10’ respectively for MLC PCM. In addition, for MLC STT-MRAM, we seeks the remapping decision that can minimize the number of the left bit flips and reduces the write of states ‘01’ and ‘10’. The experimental results show that the encoding scheme for MLC PCM saves 5.25% energy on average and the encoding scheme for MLC STT-MRAM saves 12.17% energy on average.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

Multi-level non-volatile organic transistor-based memory using lithium-ion-encapsulated fullerene as a charge trapping layer

We report on multi-level non-volatile organic transistor-based memory using pentacene semiconductor and a lithium-ion-encapsulated fullerene (Li+@C60) as a charge trapping layer. Memory organic field-effect transistors (OFETs) with a Si++/SiO2/Li+@C60/Cytop/Pentacene/Cu structure exhibited a performance of p-type transistor with a threshold voltage (Vth) of −5.98 V and a mobility (μ) of 0.84 cm2 V−1 s−1. The multi-level memory OFETs exhibited memory windows (ΔVth) of approximate 10 V, 16 V, and 32 V, with a programming gate voltage of 150 V for 0.5 s, 5 s, and 50 s, and an erasing gate voltage of −150 V for 0.17 s, 1.7 s, and 17 s, respectively. Four logic states were clearly distinguishable in our multi-level memory, and its data could be programmed or erased many times. The multi-level memory effect in our OFETs is ascribed to the electron-trapping ability of the Li+@C60 layer.

Multi-level resistive switching characteristics of W/Co:TiO2/fluorine-doped tin oxide (FTO) structures

In the present work, multi-level resistive switching (RS) in W/Co:TiO2/FTO structures induced by a multi-mixed mechanism was studied. It was found that the devices could be reproducibly programmed into three non-volatile resistance states. And the directly switching between any resistance states was realized. This increases the operation speed and lowers the complexity of controlling circuit of multi-level non-volatile memory.

Fabrication of resistive switching memory based on solution processed PMMA-HfOx blended thin films

In this study, we developed PMMA-HfOx blended resistive random access memory (ReRAM) devices using solution processing to overcome the drawbacks of the individual organic and inorganic materials. Resistive switching behaviors of solution-processed PMMA, PMMA-HfOx, and HfOx film-based ReRAM devices were investigated. The poor electrical characteristic of PMMA and brittle mechanical properties of HfOx can be improved by blending PMMA and HfOx together. The PMMA-HfOx blended ReRAM device exhibited a larger memory window, stable endurance and retention, a lower operation power, and better set/reset voltage distributions. Furthermore, these new systems featured multilevel conduction states at different reset bias for non-volatile multilevel memory applications. Therefore, solution-processed PMMA-HfOx blended films are a promising material for non-volatile memory devices on flexible or wearable electronic systems.

Nonvolatile Multilevel Memory and Boolean Logic Gates Based on a Single Ni/[Pb(Mg1/3Nb2/3)O3]0.7[PbTiO3]0.3/Ni Heterostructure

Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multi-level nonvolatile memory, we demonstrate here that nonvolatile logic gates such as NOR and NAND can be implemented in a single memtranstor made of the Ni/PMN-PT/Ni heterostructure. After applying two sequent voltage pulses (X1, X2) as the logic inputs on the memtranstor, the output magnetoelectric voltage can be positive high (logic "1"), positive low (logic "0"), or negative (logic "0"), depending on the levels of X1 and X2. The underlying physical mechanism is related to the complete or partial reversal of ferroelectric polarization controlled by inputting selective voltage pulses, which determines the magnitude and sign of the magnetoelectric voltage coefficient. The combined functions of both memory and logic could enable the memtranstor as a promising candidate for future computing systems beyond von Neumann architecture.